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JESD204 ADC Reference Design

In Detail

Lattice Reference DesignsThe LatticeECP2M provides seamless support for the JESD204 specification as it relates to high speed Analog to Digital Converters (ADCs). This standard allows front-end data acquisition to reap the benefits of a low overhead, high-speed serial link to support pure data transport.

Lattice has partnered with Linear Technology to provide a reference design using the low cost LatticeECP2M FPGA, a Lattice SERDES evaluation board, and various JESD204 compliant components from Linear Technology including a 105Msps high speed ADC. This provides designers an ideal platform for a low cost, low power and small footprint solution for FPGA based serial data acquisition and processing.

JESD204 ADC Reference Design Block Diagram

 

Deliverables:

Requires:

† Contact Linear Technology Sales for pricing and availability of the these items.

Utilization and Performance Data1 :

Configuration Resource Utilization fMAX (MHz)2
Slices REGs EBRs

With Reveal

475

453

65

164.4

Without Reveal

 132

 165

 0

 174.9

1) For ECP2M50E-6F672C using ispLEVER v7.1.  See User Guide for complete details.

2) fMAX of geared (¸2) clock.

 

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