I2C (Inter-IC) bus is a simple, low-bandwidth, short-distance protocol. It is often seen in systems with peripheral devices that are accessed intermittently. It is also a common communication solution in a close system where minimum trace on the board is desired.
This reference design implements an I2C slave module in a FPGA or CPLD. It follows the I2C specification to provide device addressing, read/write operation and an acknowledgment mechanism. It adds an instant I2C compatible interface to any component in the system. The programmable nature of FPGA and CPLD devices provides users with the flexibility of configuring the I2C slave device to any legal slave address. This avoids the potential slave address collision on an I2C bus with multiple slave devices.
| Device Family | Tested Devices* | Performance | I/O Pins | Design Size | Revision |
|---|---|---|---|---|---|
| ispMACH® 4000ZE | LC4128ZE-5 | >15MHz | 26 | 48 Macrocells | 1.3 |
| MachXO™ | LCMXO256C-3T100C | >15MHz | 26 | 57 LUTs | 1.3 |
| LatticeECP3™ | LFE3-17EA-6FTN256C | >15MHz | 26 | 69 LUTs | 1.4 |
| LatticeXP2™ | LFXP2-5E-5M132C | >15MHz | 26 | 90 LUTs | 1.4 |
| Platform Manager™ | LPTM10-12107-3FTG208CES | >15MHz | 26 | 57 LUTs | 1.3 |
download design documentation (RD1054)
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
© Lattice Semiconductor Corporation 2013
