This reference design is based on the OpenCores I2C master core and provides a bridge between the I2C and WISHBONE bus. A typical application of this design includes the interface between a WISHBONE compliant on-board microcontroller and multiple I2C peripheral components. The I2C master core generates the clock and is responsible for the initiation and termination of each data transfer.
| Tested Devices* | Language | Performance | I/O Pins | Design Size | Revision |
|---|---|---|---|---|---|
| LCMXO2-1200HC-4TG100CES | Verilog | >50MHz | 29 | 242 LUTs | 1.3 |
| LCMXO2-1200HC-4TG100CES | VHDL | >50MHz | 29 | 237 LUTs | 1.3 |
| LCMXO256C-3T100C | Verilog | >50MHz | 29 | 239 LUTs | 1.3 |
| LCMXO256C-3T100C | VHDL | >50MHz | 29 | 234 LUTs | 1.3 |
| LFE3-17EA-6FTN256C | Verilog | >50MHz | 29 | 253 LUTs | 1.4 |
| LFE3-17EA-6FTN256C | VHDL | >50MHz | 29 | 240 LUTs | 1.4 |
| LFXP2-5E-5M132C | Verilog | >50MHz | 29 | 255 LUTs | 1.4 |
| LFXP2-5E-5M132C | VHDL | >50MHz | 29 | 286 LUTs | 1.4 |
download design documentation (RD1046)
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
© Lattice Semiconductor Corporation 2012
