This reference design is intended to demonstrate how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device. With the flexibility that this I2C-Bus Master Controller offers, a designer can communicate with up to 128 different I2C slave devices operating in standard or fast mode with transactions ranging from 1 to 256 bytes. The user can also customize the VHDL code to meet their own specific requirements and thus reduce valuable CPLD/FPGA area while maintaining the speed performance they have come to expect from Lattice devices. This design conforms to the Philips I2C Bus Specification version 1.0.
| Device Family | Tested Devices* | Performance | I/O Pins | Utilization | Revision |
|---|---|---|---|---|---|
| LatticeECP3™ 1 | LFE3-17EA-6FTN256C | >33MHz | 18 | 189 LUTs | 5.6 |
| MachXO2™ 1 | LCMXO2-256HC-4TG100C | >33MHz | 18 | 191 LUTs | 5.6 |
| MachXO™ 1 | LCMXO256C-3T100C | >33MHz | 18 | 184 LUTs | 5.6 |
| LatticeXP2™ 1 | LFXP2-5E-5M132C | >33MHz | 18 | 191 LUTs | 5.6 |
| ispMACH® 4000ZE2 | LC4256ZE-5TN144C | >33MHz | 18 | 154 Macrocells | 5.6 |
| Platform Manager™ 3 | LPTM10-1247-3TG128CES |
>33MHz |
18 | 184 LUTs | 5.6 |
1. Performance and utilization characteristics generated using the specified test device and Lattice Diamond™ 1.2 software.
2. Performance and utilization characteristics generated using the specified test device with ispLEVER Classic 1.4 software.
3. Performance and utilization characteristics generated using the specified test device with ispLEVER 8.1 SP1 software (Starter or full license version)
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
© Lattice Semiconductor Corporation 2012
