This I2C Bus controller provides an interface between standard microprocessors and I2C Serial EEPROM devices. It is intended to be a simple controller providing random reads cycles only. SDRAM modules implement a Serial EPROM that supports the I2C protocol. Typically, serial EPROMS are programmed at board assembly time and store configuration information, which is read by a microprocessor during power-up. This design assumes the reader has experience with I2C controllers. This design conforms to the Philips I2C Bus Specification version 1.0.
| Tested Devices* | Language | Performance | I/O Pins | Design Size | Revision |
|---|---|---|---|---|---|
| LCMXO2-1200HC-6TG144CES | Verilog | >50MHz | 18 | 89 LUTs | 2.4 |
| LCMXO2-1200HC-6TG144CES | VHDL | >50MHz | 18 | 86 LUTs | 2.4 |
| LCMXO256E-3T100C | Verilog | >50MHz | 18 | 86 LUTs | 2.4 |
| LCMXO256E-3T100C | VHDL | >50MHz | 18 | 83 LUTs | 2.4 |
| LC4256ZE-5TN100C | Verilog | >50MHz | 18 | 64 Macrocells | 2.4 |
| LC4256ZE-5TN100C | VHDL | >50MHz | 18 | 64 Macrocells | 2.4 |
| LFE3-17EA-6FTN256C | Verilog | >50MHz | 18 | 88 LUTs | 2.5 |
| LFE3-17EA-6FTN256C | VHDL | >50MHz | 18 | 92 LUTs | 2.5 |
| LFXP2-5E-5M132C | Verilog | >50MHz | 18 | 89 LUTs | 2.5 |
| LFXP2-5E-5M132C | VHDL | >50MHz | 18 | 87 LUTs | 2.5 |
download design documentation (RD1006)
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
© Lattice Semiconductor Corporation 2013
