HDLC is the abbreviation for High-Level Data Link Control published by the International Standards Organization (ISO). This data link protocol is located at the link layer (layer 2) of the 7-layer OSI reference model. Today, a variety of link layer protocols such as LAPB, LAPD, LLC and SDLC are all based on the HDLC protocol with a few modifications.
The netlist files for CPLDs include .BL1 files for ispMACH 4000ZE, 4000, and 5000VG, .LD1 files for ispXPGA, and .NGO files for ORCA family support. The netlist files for FPGAs include .NGO files.
| Family | Device | Channels Configured | LUTs | REGs | SLICEs | fmax (MHz)1 | Revision |
|---|---|---|---|---|---|---|---|
|
ECP2 |
LFE2-70E-5F672C |
1 |
104 |
140 |
95 |
88 |
1.1 |
|
6 |
701 |
855 |
602 |
193 |
1.1 | ||
|
ECP2M |
LFE2M-70E-5F900C |
1 |
104 |
140 |
95 |
292 |
1.1 |
|
6 |
701 |
855 |
602 |
158 |
1.1 | ||
|
XP2 |
LFXP2-17E-5F256C |
1 |
104 |
140 |
95 |
292 |
1.1 |
|
6 |
701 |
855 |
602 |
163 |
1.1 | ||
|
MachXO |
LCMXO2280C5FT324C |
1 |
105 |
140 |
76 |
227 |
1.1 |
|
6 |
698 |
855 |
477 |
149 |
1.1 |
1. The Max. Clock Frequency is obtained by running the Timing Analysis of Lattice design software. Please run the timing simulation after you merge it with your design.
Download design documentation (RD1038)
| Tested Devices | Performance | I/O Pins |
Design Size | Revision |
|---|---|---|---|---|
|
Multiple Channels |
||||
|
LC51024VG-5F676 |
81.3 MHz |
|
970/1024 Macrocells |
3.1 |
|
Single Channel |
||||
|
LC4256B-3T176C |
270.3 MHz |
|
149/256 Macrocells |
3.1 |
|
LC4256ZE-7MN144C |
155.04 MHz |
|
142/256 Macrocells |
3.1 |
1. The Max. Clock Frequency is obtained by running the Timing Analysis of Lattice design software. Please run the timing simulation after you merge it with your design.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
© Lattice Semiconductor Corporation 2012
