This CompactFlash Controller reference design is used to interface a CompactFlash with a WISHBONE bus compatible host. It is located between the CompactFlash and the WISHBONE bus master and is intended to reduce the amount of effort necessary for the user to deal with the ATA/IDE command. The CompactFlash controller responds to read/write cycles started by the wishbone bus host. The controller functions as a data path controller, transferring data to and from the WISHBONE bus host onto the CompactFlash. The design demonstrates how a configurable CompactFlash interface controller can be constructed and utilized in a Lattice CPLD/FPGA device.
The controller design offers the following features:
The user can also customize the source code to meet their own specific requirements and thus reduce valuable CPLD/FPGA area while maintaining the speed performance they have come to expect from Lattice devices.
| Tested Devices* | Language | Performance | I/O Pins | Design Size | Revision |
|---|---|---|---|---|---|
| LCMXO2-1200HC-6TG144CES | Verilog | >100MHz | 68 | 173 LUTs, 2EBR | 1.3 |
| LCMXO2-1200HC-6TG144CES | VHDL | >100MHz | 68 | 174 LUTs, 2EBR | 1.3 |
| LCMXO2280C-5T100C | Verilog | >100MHz | 68 | 629 LUTs, 1 EBR | 1.3 |
| LCMXO2280C-5T100C | VHDL | >100MHz | 68 | 626 LUTs, 1EBR | 1.3 |
| LFXP2-5E-5TN144C | Verilog | >100MHz | 68 | 732 LUTs, 1 EBR | 1.3 |
| LFXP2-5E-5TN144C | VHDL | >100MHz | 68 | 730 LUTs, 1EBR | 1.3 |
download design documentation (RD1040)
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
© Lattice Semiconductor Corporation 2012
