Synchronous DRAM (SDRAM) has become a mainstream memory of choice in embedded system memory design due to its speed. This SDRAM controller reference design, located between the SDRAM and the bus master, reduces the user's effort to deal with the SDRAM command interface by providing a simple generic system interface to the bus master.
| Tested Devices* | Language | Performance | I/O Pins |
Design Size |
Design Size |
Revision |
|---|---|---|---|---|---|---|
| LCMXO2-1200HC-5TG144CES | Verilog | > 60 MHz | 73 | 117 LUTs | 118 LUTs | 4.5 |
| LCMXO2-1200HC-5TG144CES | VHDL | > 60 MHz | 73 | 110 LUTs | 107 LUTs | 4.5 |
| LFE3-95EA-7FN1156C | Verilog | > 60 MHz | 73 | 115 LUTs | 4.6 | |
| LFE3-95EA-7FN1156C | VHDL | > 60 MHz | 73 | 115 LUTs | 4.6 | |
| LFXP20-5E-5FT256C | Verilog | > 100 MHz | 73 | 159 LUTs | 135 LUTs | 4.6 |
| LFXP20-5E-5FT256C | VHDL | > 100 MHz | 73 | 120 LUTs | 124 LUTs | 4.6 |
| LCMXO2280C-3 | Verilog | > 60 MHz | 73 | 117 LUTs | 118 LUTs | 4.5 |
| LCMXO2280C-3 | VHDL | > 60 MHz | 73 | 109 LUTs | 107 LUTs | 4.5 |
| LFECP33-5 | Verilog | > 100 MHz | 73 | 159 LUTs | 135 LUTs | 4.5 |
| LFECP33-5 | VHDL | > 100 MHz | 73 | 120 LUTs | 124 LUTs | 4.5 |
| ispLSI 5512VE-155 | Verilog | > 100 MHz | 73 | None | 84 macrocells | 4.5 |
| ispLSI 5512VE-155 | VHDL | > 100 MHz | 73 | None | 84 macrocells | 4.5 |
| LC4256ZE-5 | Verilog | > 100 MHz | 73 | None | 84 Macrocells | 4.5 |
| LC4256ZE-5 | VHDL | > 100 MHz | 73 | None | 84 macrocells | 4.5 |
| LFXP2-5E-5FT256C | Verilog | > 100 MHz | 73 | 169LUTs | 133 LUTs | 4.5 |
| LFXP2-5E-5FT256C | VHDL | > 100 MHz | 73 | 149 LUTs | 133 LUTs | 4.5 |
download design documentation (RD1010)
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
© Lattice Semiconductor Corporation 2013
