8-bit Microcontroller - LatticeMico8

The LatticeMico8 is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice. Combining a full 18-bit wide instruction set with 32 General Purpose registers, the LatticeMico8 is a flexible reference design written in Verilog and VHDL suitable for a wide variety of markets, including communications, consumer, computer, medical, industrial, and automotive. The core consumes minimal device resources, less than 200 Look Up Tables (LUTs) in the smallest configuration, while maintaining a broad feature set.

The LatticeMico8 is licensed under a new open intellectual property (IP) core license, the first such license offered by any FPGA supplier. The main benefits of using open source IP are greater flexibility, improved portability, and no cost. This new agreement provides all the benefits of standard open source and allows users to mix proprietary designs with the open source core. Additionally, it allows for the distribution of designs in bitstream or FPGA format without accompanying it with a copy of the license.

Contribute to the LatticeMico8! Do you have designs you would like to share with us? Have you come across a bug? Is there a new feature you would like to see? Let us know! Send an email to Technical Support at techsupport@latticesemi.com.

Features

• 8-bit Data Path
• 18-bit Wide Instructions
• Configurable 16 or 32 General Purpose Registers
• Input/Output is Performed Using "Ports" (256 Ports/page, up to 65536 pages)
• Optional 256 bytes of External Scratch Pad RAM
• Two Cycles Per Instruction
• Three cycles per Input/Output cycle (extendable using READY strobe)
• Lattice UART Reference Design Peripheral

Evaluation Configurations

The following table shows a few of the many possible configurations. The v3.0 Mico8 core can be targeted to any Lattice FPGA.

* SP = Scratch Pad

Documentation

LatticeMico8 User Guide

Development Kit Demonstrations

Mini System-on-Chip Demo for MachXO Mini Development Kit, EB41 MachXO Mini Development Kit User's Guide

Control System-on-Chip Demo for MachXO Control Development Kit, EB46 MachXO Control Development Kit User's Guide

Technote 1095 - Using the LatticeMico8 Microcontroller with the LatticeXP Evaluation Board

Core Code

Version 3.0 of the LatticeMico8 increases addressable code space, has configurable address range and improved stack operations for support of high-level compilers, while keeping a very small footprint.  The code will run on ispLever 5.1 and later. The predefined ispLever project (i.e. .syn) files are valid for 7.0 and later.

LatticeMico8 Core Source Code Revision 3.0 Verilog - NEW

LatticeMico8 Core Source Code Revision 3.0 VHDL - NEW

Tool Code

LatticeMico8 Tools Code for Core Revision 3.0 and above
The above tools package contains both the source code and the executable files for the LatticeMico8

Demo

LatticeMico8 Demo

Useful External Links

• AS Assembler maintained by Alfred Arnold
  Another assembler that supports the LatticeMico8

Archived Code

LatticeMico8 Core Source Code Revision 2.4 Verilog
The above source code is the VHDL source code for ispLEVER version 6.0 and above.

LatticeMico8 Core Source Code Revision 2.4 VHDL
The above source code is the VHDL source code for ispLEVER version 6.0 and above.

LatticeMico8 Core Source Code Revision 2.3 Verilog
The above Verilog source code supports the LatticeECP2, the LatticeECP/EC, LatticeXP, and MachXO devices.  Additionally, this version handles a larger number of instructions (1024 for LatticeECP2) and supports a bigger jump/branch (2048). For new designs, it is recommended to use Revision 2.4.

LatticeMico8 Core Source Code Revision 2.3 VHDL
The above VHDL source code supports the LatticeECP2, the LatticeECP/EC, LatticeXP, and MachXO devices.  Additionally, this version handles a larger number of instructions (1024 for LatticeECP2) and supports a bigger jump/branch (2048). For new designs, it is recommended to use Revision 2.4.

LatticeMico8 Core Source Code Revision 2.2 Verilog Only
The above source code has a couple of bug fixes and has been fully tested for the MachXO family of Crossover Programmable Logic devices.

LatticeMico8 Core Source Code Revision 1.0 Verilog Only

LatticeMico8 Tools Code for Core Revision 2.3

LatticeMico8 Tools Code Revision 1.0