Many serial data transmission standards utilize 8b/10b encoding to ensure sufficient data transitions for clock recovery. This reference design describes an encoder/decoder suitable for performing 8b/10b encoding/decoding within Lattice programmable logic devices. Several generic CPLD and FPGA implementations are shown with this reference design.
| Tested Devices* | Design Size | Performance | I/O Pins | Revision |
|---|---|---|---|---|
| LCMXO1200C-3T100C | 152 LUTs | >100 MHz | 43 | 1.1 |
| LFE3-150EA-7FN1156C | 184 LUTs | > 200 MHz | 43 | 1.2 |
| LFE2M-50E-6F672C | 184 LUTs | > 200 MHz | 43 | 1.2 |
| LFECP-6E-5T144C | 184 LUTs | >100 MHz | 43 | 1.2 |
| LFXP2-5E-5M132C | 184 LUTs | > 100 MHz | 43 | 1.2 |
| LC4256B-3T100C | 74 Macrocells | >90 MHz | 43 | 1.1 |
| LC51024MB-52F484C | 73 Macrocells | >90 MHz | 43 | 1.1 |
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
© Lattice Semiconductor Corporation 2013
