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The 7:1 source synchronous LVDS interface (also known as Channel Link, Flat Link, and Camera Link) is commonly used in video display applications such as consumer electronics, industrial control, medical imaging, and automotive telematics. Lattice's 7:1 LVDS Video Interface Reference Design has been optimized for use with the LatticeECP2/M family of FPGAs. The reference design implements standard 7:1 LVDS interfaces using the LatticeECP2/M I/O structure. Transmit and receive interfaces are fully and efficiently implemented by specifically taking advantage of dedicated LVDS I/O, the generic DDR I/O interface, 2x gearing, and PLL clocking of edge and system clocks. Data formatting is also accomplished using dedicated 4:7 deserializer modules.
Performance and Resource Utilization
Design 1 Results for LatticeECP2/M1 - Loopback Test
| Date |
Language |
SLICEs |
LUTs |
Registers |
sysMEM EBRs |
sysDSP™ Blocks |
fMAX(MHz) |
April 2007
|
VHDL |
900 (3.75%)
|
846 |
961 |
0 (0%)
|
0 (0%) |
85 |
| April 2007 |
Verilog |
903 (3.76%)
|
856 |
957 |
0 (0%)
|
0 (0%) |
85 |
Design 2 Results for LatticeECP2/M1 - Video Processing Design
| Date |
Language |
SLICEs |
LUTs |
Registers |
sysMEM EBRs |
sysDSP™ Blocks |
fMAX(MHz) |
April 2007
|
VHDL |
1559 (6.50%)
|
1820 |
1371 |
8 (38%) |
4.125 (23%) |
108 |
| April 2007 |
Verilog |
1552 (6.47%)
|
1824 |
1281 |
8 (38%) |
4.125 (23%) |
108 |
Lattice 7:1 LVDS Video Demo Kit
The Lattice 7:1 LVDS Video Demo Kit is a set of boards and cables that demonstrate the implementation of a 7:1 LVDS solution using the LatticeECP2 FPGA. The kit works with the LatticeECP2-Advanced Evaluation Board (or an equivalent), as well as various user video I/O resources.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
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