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7:1 LVDS Video Interface

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Source synchronous interfaces consisting of multiple data bits and clocks have become a common method for moving image data within electronic systems. A prevalent standard is the 7:1 LVDS interface (employed in Channel Link, Flat Link, and Camera Link), which has become a common standard in many electronic products including consumer devices, industrial control, medical, and automotive telematics.  Lattice's 7:1 LVDS Video Interface Reference Design has been optimized for use with the LatticeECP3, LatticeECP2/M, and LatticeXP2 FPGA families.  The reference design implements standard 7:1 LVDS interfaces using the FPGA I/O structure.  Transmit and receive interfaces are fully and efficiently implemented by specifically taking advantage of dedicated LVDS I/O, the generic DDR I/O interface, gearing, and PLL clocking of edge and system clocks.  Data formatting is also accomplished using dedicated deserializer modules.

7:1 LVDS Receiver and Transmitter

Performance and Resource Utilization

Design 1: Results for Loopback Test
Date Family Language SLICEs LUTs Registers sysMEM EBRs sysDSP™ Blocks fMAX(MHz)
Aug 2009 ECP3-95 VHDL 794 862 (1%) 930 0 (0%) 0 (0%) 135
Aug 2009 ECP3-95 Verilog 791 861 (1%) 930 0 (0%) 0 (0%) 135
Aug 2009 ECP2/M-50 VHDL 979 1169 (2%) 1036 0 (0%) 0 (0%) 108
Aug 2009 ECP2/M-50 Verilog 995 1182 (2%) 1032 0 (0%) 0 (0%) 108
Aug 2009 XP2-17 VHDL 805 857 (5%) 887 0 (0%) 0 (0%) 108
Aug 2009 XP2-17 Verilog 800 854 (5%) 887 0 (0%) 0 (0%) 108

Performance and utilization characteristics are generated using Lattice ispLEVER® 7.0 SP1 software for LatticeECP2/M and LatticeXP2 devices, and ispLEVER7.2 SP2 software for LatticeECP3 devices. When using this IP core in a different density, speed, or grade within the LatticeECP2/M, LatticeXP2 and LatticeECP3 families, performance and utilization may vary.

Design 2: Results for Video_Demo Test
Date Family Language SLICEs LUTs Registers sysMEM EBRs sysDSP™ Blocks fMAX(MHz)
Aug 2009 ECP3-95 VHDL 1423 1832 (2%) 1351 8 (3%) 6.625 (21%) 108
Aug 2009 ECP3-95 Verilog 1430 1879 (2%) 1291 10 (4%) 6.625 (21%) 108
Aug 2009 ECP2/M-50 VHDL 1647 2140 (4%) 1390 8 (38%) 4.125 (23%) 108
Aug 2009 ECP2/M-50 Verilog 1629 2156 (4%) 1354 8 (38%) 4.125 (23%) 108
Aug 2009 XP2-17 VHDL 1492 1866 (11%) 1300 10 (67%) 4.125 (83%) 108
Aug 2009 XP2-17 Verilog 1482 1897 (11%) 1263 10 (67%) 4.125 (83%) 108

Note: Performance and utilization characteristics are generated using Lattice ispLEVER 7.0 SP1 software for LatticeXP2 and LatticeECP2/M devices, and ispLEVER 7.2 SP2 software for LatticeECP3 devices. When using this IP core in a different density, speed, or grade within the LatticeECP2/M, LatticeXP2 and LatticeECP3 families, performance and utilization may vary.

 

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PDF file Download design documentation
EXE files Download source code

 

Lattice 7:1 LVDS Video Demo Kit

The Lattice 7:1 LVDS Video Demo Kit is a set of boards and cables that demonstrate the implementation of a 7:1 LVDS solution using the LatticeECP2 or LatticeXP2 FPGA. The kit works with the LatticeECP2 or LatticeXP2 Advanced evaluation boards, as well as various user video I/O resources.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.