RapidIO 1x LP-Serial Physical Layer Core for LatticeECP2M

Overview

The RapidIO Interconnect Architecture is an industry-standard, packet-based interconnect technology that provides a reliable, high-performance interconnect between NPUs (network processing units), CPUs (central processing units), and DSPs (digital signal processors).  Serial RapidIO enables chip-to-chip, board-to-board, and system-to-system communications and is targeted at the networking, embedded, and storage markets. 

Praesum Communications' Serial RapidIO core is a complete high-performance solution that implements required physical layer (PHY) functionality defined in the RapidIO Physical Layer 1x/4x LP-Serial Specification Revision 1.3.  In addition to PHY layer functions, the core's Management Module supports access to Physical, Transport, and Logical Layer CSRs through maintenance transactions or through the built-in Alternate Management Interface (AMI).  The Management Module includes an interface which enables a processor to transmit or receive RapidIO packets, and permits system-level testing, or easy implementation of logical layer functions in software.  Advanced features, such as the optional RapidIO Error Management Extensions, are also supported.

The core is architected for performance and optimal resource utilization of the LatticeECP2M architecture, consuming between only 50-70% of the smallest device, depending on the features implemented.   As a result, the solution enables significant device resources for customer applications such as bridging to data plane or control plane interfaces. such as CPRI or PCI Express respectively.   When combined with LatticeECP2M device features such as small scale packaging, low power consumption, and high-speed SERDES resources, the Praesum solution offers compelling value for multiple markets including digital signal processing, embedded computing, military/aerospace, and communications infrastructure.

Praesum Serial RapidIO 1x Physical Layer Core Block Diagram

Implementation Results

The following are typical performance and utilization results.

¹ Performance and utilization characteristics are generated using an LFE2M-20E-6F256C. When using this IP core in a different density, package, speed, or grade within the LatticeECP2M family, performance and utilization may vary.

Features

• Implements the complete RapidIO 1x/4x Physical Layer LP-Serial protocol for 1x links
• Compliant with RapidIO Rev 1.3 specifications
• 1.2 GHz, 2.5 GHz, and 3.125 GHz serial specification support
• Optional RapidIO Error Management Extensions support
  
• 64-bit datapaths
• Integrated buffer module for transmit and receive packet buffering
• Supports up to four ports for logical layer functions