Serial RapidIO x1 and x4 Endpoint Cores

Overview

The RapidIO Interconnect Architecture is an industry-standard, packet-based interconnect technology that provides a reliable, high-performance interconnect between NPUs (network processing units), CPUs (central processing units), and DSPs (digital signal processors).  Serial RapidIO enables chip-to-chip, board-to-board, and system-to-system communications and is targeted at the networking, embedded, and storage markets. 

Mercury Computer Systems' Serial RapidIO core is a complete high-performance solution, high-function core, that incorporates a logical layer, transport layer, and physical layer.  It supports input/output and message-passing logical layer standards, and is capable of addressing a variety of solutions, including endpoint and switching applications.

The core is architected to enable an end-to-end solution for designers who wish to target Lattice FPGAs, and it can also be designed into multi-port switches.  It provides a Serial RapidIO interface on one side and a simple implementation-neutral user interface on the other to ease the construction of other interfaces.  The Serial RapidIO core is ideal for use in a variety of communication applications including base stations, edge routers, RNCs, enterprise switches, and other devices requiring a high-speed interface.  It can also be incorporated into high-end embedded computing applications.

Serial RapidIO Architecture

Implementation Results

The following are typical performance and utilization results.

Features

• 1.2 GHz, 2.5 GHz, and 3.125 GHz serial specification support
• Endpoint and switch application support
• x1 and x4 serial interface support
• Error management extensions
• 34-bit addressing
• Legal data payload sizes up to 256 bytes
• All transaction flows and priorities
• Input/output and message-passing protocols
• Advanced buffer management scheme
• Receiver-controlled and transmitter-based flow control
• Multicast event support
• Compliant with RapidIO specification, revision 1.2