XAUI - 10Gb Ethernet Attachment Unit Interface

Overview

10Gb Ethernet Attachment Unit Interface or XAUI is a high-speed interconnect that offers reduced pin count and has the ability to drive up to 20 inches of PCB trace on standard FR-4 material. Each XAUI interface comprises four self-timed 8b10b encoded serial lanes each operating at 3.125 Gbps and thus is capable of transferring data at an aggregate rate of 10 Gbps. 

XAUI IP Core provides a solution for bridging between XAUI and 10 Gigabit Media Independent Interface (XGMII) devices. This IP core implements 10Gb Ethernet Extended Sublayer (XGXS) capabilities in soft logic that together with PCS and SERDES functions implemented in the FGPA provides a complete XAUI-to-XGMII solution.

XAUI Protocol Stack 

Block Diagram

Features

• XAUI compliant functionality supported by embedded SERDES PCS functionality implemented in the LatticeECP2M and LatticeECP3, including four channels of 3.125 Gbps serializer/deserializer with 8b10b encoding/decoding.
• Complete 10Gb Ethernet Extended Sublayer (XGXS) solution based on LatticeECP2M and LatticeECP3 FPGA.
• Soft IP targeted to the FPGA implements XGXS functionality conforming to IEEE 802.3ae-2002, including:
  • 10 GbE Media Independent Interface (XGMII).
  • Optional Slip buffers for clock domain transfer to/from the XGMII interface.
  • Complete translation between XGMII and XAUI PCS layers, including 8b10b encoding and decoding of Idle, Start, Terminate, Error and Sequence code groups and sequences, and randomized Idle generation in the XAUI transmit direction.
  • XAUI compliant lane-by-lane synchronization.
  • Lane deskew functionality.
  • Interface with the high-speed SERDES block embedded in the LatticeECP2M and LatticeECP3 that implements a standard XAUI.
  • Optional standard compliant MDIO/MDC interface.
• Aldec and ModelSim simulation models and test benches provided for free evaluation.

Lattice's IP hardware evaluation capability makes it possible to create versions of IP cores that operate in hardware for a limited time of four hours without requiring the purchase on an IP license. The hardware evaluation capability is turned on by enabling the Hardware Evaluation option in the properties of the Build Database process in ispLEVER.  If a license is detected, core generation is completed with no restrictions.

Performance and Resource Utilization

1. Performance and utilization data are generated using Lattice Diamond 1.0 and Synplify Pro for Lattice D-2009.12L software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family.

1. Performance and utilization data are generated using Lattice Diamond 1.0 and Synplify Pro for Lattice D-2009.12L software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2M family.

Demos

• LatticeECP3 XAUI Demo

Ordering Information

IP Version: 1.6
Evaluate: To download a full evaluation version of this IP, go to the IPexpress tool and click the IP Server button in the toolbar. All LatticeCORE IP cores and modules available for download will be visible.  For more information on viewing/downloading IP please read the IP Express Quick Start Guide.
Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.