Turbo Encoder

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Overview

Turbo coding is an advanced error correction technique widely used in the communications industry. Turbo encoders and decoders are key elements in today's communication systems to achieve the best possible data reception with least possible errors. The basis of turbo coding is to introduce redundancy in the data to be transmitted through a channel. The redundant data helps to recover original data from the received data.

Lattice's Turbo Encoder IP Core is compliant with three different standards: 3GPP, 3GPP2, and CCSDS. The 3GPP and 3GPP2 standards are widely used in WCDMA and MC-CDMA applications while CCSDS is most commonly found in telemetry and space communications. Each one of these encoders is a separate entity as the interleaver and control logic for each encoder is completely different.

Lattice's Turbo Encoder core is created in conjunction with the Turbo Decoder core to provide users with a state of the art error correction technique.

Features

Fully compatible with the following standards:
- 3GPP TS 25.212 Version 4.2.0
- 3GPP2 C.S0002-A
- CCSDS 101.0-B-5
Up to 60 MHz clock speed
Variable input block sizes
User defined number of states
Fixed processing delay of 12 cycles for CCSDS, 10 cycles for 3GPP, and 9 cycles for 3GPP2.
User parameterized forward and backward polynomials
Programmable puncturing support
IP Core Package Contains
- Data Sheet and User's Guide
- Lattice Netlist and Secured Simulation Model
- Behavioral Testbench

Performance and Utilization Results

Results for ORCA4¹
Parameter File	Mode	ORCA4 PFUs	LUTs	Registers	I/Os	EBR	Fmax (MHz)
turbo_enco_o4_1_001.lpc	3GPP	328	1774	694	23	N/A	62
turbo_enco_o4_1_002.lpc	3GPP2	107	555	324	25	N/A	70
turbo_enco_o4_1_003.lpc	CCSDS	97	250	393	24	N/A	66

¹ Performance and utilization characteristics are generated targeting OR4E02-2BA352 in ispLEVER^TM v.3.0 software. Evaluation configurations are included in the table above.

Results for ispXPGA¹
Parameter File	Mode	ispXPGA PFUs	LUTs	Registers	I/Os	EBRs	Fmax (MHz)
turbo_enco_xp_1_001.lpc	3GPP	469	1222	550	23	6	61 MHz
turbo_enco_xp_1_002.lpc	3GPP2	268	780	354	25	6	64 MHz
turbo_enco_xp_1_003.lpc	CCSDS	208	432	436	24	4	93 MHz

¹ Performance and utilization characteristics are generated targeting an LFX500B-04F516C in ispLEVER software v.3.0, Service Pack 2. Evaluation configurations are included in the table above.

Results for LatticeECP/EC™¹
IPexpress User-Configurable Mode	SLICEs	LUTs	Registers	I/Os	sysMEM EBRs	Fmax (MHz)
3GPP	692	1363	452	23	4	99
3GPP2	352	678	320	25	4	123
CCSDS	263	492	384	24	2	177

¹ Performance and utilization characteristics are generated using LFEC20E-5F672C in Lattice’s ispLEVER v.7.1 SP1 software. When using this IP core in a different device, density, package, or speed grade, performance may vary.

Results for LatticeECP2™¹
IPexpress User-Configurable Mode	SLICEs	LUTs	Registers	I/Os	sysMEM EBRs	Fmax (MHz)
3GPP	691	1365	450	23	4	135
3GPP2	356	686	322	25	4	202
CCSDS	275	516	378	24	2	256

¹ Performance and utilization characteristics are generated using LFE2-20E-5F672C in Lattice’s ispLEVER v.7.1 SP1 software. When using this IP core in a different device, density, package, or speed grade, performance may vary.

Results for LatticeECP2M™¹
IPexpress User-Configurable Mode	SLICEs	LUTs	Registers	I/Os	sysMEM EBRs	Fmax (MHz)
3GPP	691	1365	450	23	4	143
3GPP2	356	686	322	25	4	204
CCSDS	275	516	378	24	2	246

¹ Performance and utilization characteristics are generated using LFE2M-35E-7F484C in Lattice’s ispLEVER v.7.1 SP1 software. When using this IP core in a different device, density, package, or speed grade, performance may vary.

Results for LatticeXP™¹
IPexpress User-Configurable Mode	SLICEs	LUTs	Registers	External Pins	sysMEM EBRs	Fmax (MHz)
3GPP	692	1363	452	23	4	94
3GPP2	352	578	320	25	2	123
CCSDS	263	492	384	24	1	177

¹ Performance and utilization characteristics are generated using LFXP20E-5F484C in Lattice’s ispLEVER v.7.1 SP1 software. When using this IP core in a different device, density, package, or speed grade, performance may vary.

Results for LatticeXP2™¹
IPexpress User-Configurable Mode	SLICEs	LUTs	Registers	External Pins	sysMEM EBRs	Fmax (MHz)
3GPP	691	1365	450	23	4	119
3GPP2	356	686	322	25	2	176
CCSDS	275	516	378	24	1	222

¹ Performance and utilization characteristics are generated using LFXP2-17E-7F484C in Lattice’s ispLEVER v.7.1 SP1 software. When using this IP core in a different device, density, package, or speed grade, performance may vary.

Results for LatticeSC™¹
IPexpress User-Configurable Mode	SLICEs	LUTs	Registers	External Pins	sysMEM EBRs	Fmax (MHz)
3GPP	691	1349	448	23	4	184
3GPP2	361	690	322	25	2	220
CCSDS	275	516	386	24	1	325

¹ Performance and utilization characteristics are generated using LFSC3GA25E-7F900C in Lattice’s ispLEVER v.7.1 SP1 software. When using this IP core in a different device, density, package, or speed grade, performance may vary.

Ordering Information

Part Numbers:
For ORCA4: TURBO-ENCO-O4-N1
For ispXPGA: TURBO-ENCO-XP-N1
For LatticeECP/EC: TURBO-ENCO-E2-U3
For LatticeECP2: TURBO-ENCO-P2-U3
For LatticeECP2M: TURBO-ENCO-PM-U3
For LatticeXP: TURBO-ENCO-XM-U3
For LatticeXP2: TURBO-ENCO-X2-U3
For LatticeSC: TURBO-ENCO-SC-U3

To find out how to purchase the Turbo Encoder IP Core, please contact your local Lattice Sales Office.