Turbo Decoder

Overview

Turbo coding is an advanced error correction technique widely used in the communications industry. Turbo encoders and decoders are key elements in today's communication systems to achieve the best possible data reception with the fewest possible errors. The basis of turbo coding is to introduce redundancy in the data to be transmitted through a channel. The redundant data helps to recover original data from the received data. In data transmission, turbo coding helps achieve near Shannon limit performance.

Lattice provides a Turbo Decoder IP core that is both flexible and compliant with two different standards, 3GPP and CCSDS. 3GPP is widely used in WCDMA and MC-CDMA applications while CCSDS is most commonly found in telemetry and space communications.

Lattice also supplies users with a Turbo Encoder core providing users a complete state of the art error correction solution.

Features

• Compliant with Standards:
  • 3GPP TS 25.212 version 4.2.0
  • CCSDS 101.0-B-5
• Throughput of 2Mbps for 3GPP at 30MHz, 7 Iterations
• Two's Complement Data/Parity Input
• Supports Depuncturing
• Variable Soft-Widths for Input Symbols, Branch Metrics, Path Metrics and LLRs
• User-Defined Number of States
• Variable Block Sizes During Runtime
• Programmable Number of Iterations
• Optional Hard Decision Storage
• Selectable Max-Log-Map or Log-Map Algorithm
• Programmable Pipe Stages for Convenient Memory Interfacing
• Optional Double Buffering

Performance and Utilization

Results for ORCA4¹

Parameter File	Mode	ORCA4 PFUs	LUTs	Registers	PIO	EBR	Fmax
turbo_deco_o4_1_001.lpc	3GPP	1235	3750	3569	184	N/A	46 MHz
turbo_deco_o4_1_003.lpc	CCSDS	1674	3292	4807	191	N/A	36 MHz

¹ Performance and utilization characteristics are generated targeting an OR4E06-2BA352 in ispLEVER^TM v.3.0 software.

Results for ispXPGA¹

Parameter File	Mode	ispXPGA PFUs	LUTs	Registers	PIO	EBR	Fmax
turbo_deco_xp_1_001.lpc	3GPP	2167	4586	3628	184	32	52 MHz
turbo_deco_xp_1_003.lpc	CCSDS	3486	5834	4966	269	49	46 MHz

¹ Performance and utilization characteristics are generated targeting an LFX1200B-04FE680C in ispLEVER^TM v.3.0 software.

 

Results for LatticeECP™/LatticeEC™¹

IPexpress User-Configurable Mode	SLICEs	LUTs	Registers	I/Os	sysMEM" EBR	Fmax (MHz)
3GPP	2676	5230	2838	184	17	82
3GPP2	2834	5510	3020	249	49	84
CCSDS	4124	8093	4294	269	25	68

 ¹ Performance and utilization characteristics are generated using LFEC33E-5F672C with Lattice’s ispLEVER v.7.1 SP1  software. When using this IP core in a different density, speed, or grade within the LatticeECP/EC family, performance may vary.

 

Results for LatticeECP2™¹

IPexpress User-Configurable Mode	SLICEs	LUTs	Registers	I/Os	sysMEM" EBR	Fmax (MHz)
3GPP	2732	5365	2831	184	13	126
3GPP2	2801	5490	3015	249	27	124
CCSDS	4274	8433	4295	269	16	115

 ¹ Performance and utilization characteristics are generated using LFE2-70E-7F672C with Lattice’s ispLEVER v.7.1 SP1 software. When using this IP core in a different density, speed, or grade within the LatticeECP2 family, performance may vary.

 

Results for LatticeECP2M™¹

IPexpress User-Configurable Mode	SLICEs	LUTs	Registers	I/Os	sysMEM" EBR	Fmax (MHz)
3GPP	2747	5403	3085	184	13	110
3GPP2	2712	5311	3312	249	27	111
CCSDS	4238	8350	4540	269	16	100

 ¹ Performance and utilization characteristics are generated using LFE2M-35E-7F672C with Lattice’s ispLEVER v.7.1 SP1 software. When using this IP core in a different density, speed, or grade within the LatticeECP2M family, performance may vary.

 

Results for LatticeXP™¹

IPexpress User-Configurable Mode	SLICEs	LUTs	Registers	I/Os	sysMEM" EBR	Fmax (MHz)
3GPP	2744	5372	2838	184	17	76
CCSDS	4162	8268	4316	269	25	65

 ¹ Performance and utilization characteristics are generated using LFXP20E-5F484C with Lattice’s ispLEVER v.7.1 SP1 software. When using this IP core in a different density, speed, or grade within the LatticeXP family, performance may vary.  Due to memory resource limitations, 3GPP2 support is not recommended for LatticeXP.

Results for LatticeXP2™¹

IPexpress User-Configurable Mode	SLICEs	LUTs	Registers	I/Os	sysMEM" EBR	Fmax (MHz)
3GPP	2801	5490	3077	184	17	98

 ¹ Performance and utilization characteristics are generated using LFXP2-17E-5F484C with Lattice’s ispLEVER v.7.1 SP1 software. When using this IP core in a different density, speed, or grade within the LatticeXP2 family, performance may vary.  Due to memory resource limitations, 3GPP2 and CCSDS support is not recommended for LatticeXP2.

Results for LatticeSC™¹

IPexpress User-Configurable Mode	SLICEs	LUTs	Registers	I/Os	sysMEM" EBR	Fmax (MHz)
3GPP	2766	5356	2827	184	13	172
3GPP2	2747	5334	3066	249	27	197
CCSDS	4008	7791	4326	269	16	174

 ¹ Performance and utilization characteristics are generated using LFSC3GA25E-7F900C with Lattice’s ispLEVER v.7.1 SP1 software. When using this IP core in a different density, speed, or grade within the LatticeSC family, performance may vary.

 

Part Numbers:
For ORCA4: TURBO-DECO-O4-N1
For ispXPGA: TURBO-DECO-XP-N1
For LatticeECP/EC: TURBO-DECO-E2-U3
For LatticeECP2:  TURBO-DECO-P2-U3
For LatticeECP2M:  TURBO-DECO-PM-U3
For LatticeXP:  TURBO-DECO-XM-U3
For LatticeXP2:  TURBO-DECO-X2-U3
For LatticeSC:  TURBO-DECO-SC-U3

To find out how to purchase the Turbo Decoder IP Core, please contact your local Lattice Sales Office.