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Tri-Speed Ethernet MAC IP Core

In Detail

Overview

IPexpress User Configurable Logo The Tri-Speed Ethernet Media Access Controller (TSMAC) IP core can be configured to operate in either the Gigabit mode (1000Mbits/sec data rate) or the Fast Ethernet mode (10/100 Mbits/sec data rate). Operation in either Gigabit mode or Fast Ethernet mode is selected by setting an internal register bit.

The Tri-Speed Ethernet MAC transmits and receives data between a host processor and an Ethernet network. The main function of the Ethernet MAC is to ensure that the Media Access rules specified in the 802.3 IEEE standard are met while transmitting a frame of data over Ethernet. On the receiving side, the Ethernet MAC extracts the different components of a frame and transfers them to higher applications through the FIFO interface.

Tri-Speed Ethernet MAC IP Core Block Diagram

The data received from the G/MII interface is first buffered until sufficient data is available to be processed by the Receive MAC (Rx MAC). The Preamble and the Start of Frame Delimiter (SFD) information are then extracted from the incoming frame to determine the start of a valid frame. The Receive MAC checks the address of the received packet and validates whether the frame can be received before transferring it into the FIFO. Only valid frames are transferred into the FIFO. This feature has the following two benefits: the systems need not re-calculate the Frame Check Sequence (FCS) again when the frame is being transmitted, and it also keeps the receive MAC relatively simple. The Tri-Speed MAC, however, always calculates CRC to check whether the frame was received error-free.

On the transmit side, the Tx MAC is responsible for controlling access to the physical medium. The Tx MAC reads data from an external client Tx FIFO, formats this data into an Ethernet packet and passes it to the G/MII module. The Tx MAC reads data from the Tx Client FIFO when the client indicates a packet is available, and the Tx MAC is in its appropriate state. The Tx MAC pre-fixes the Preamble and the Start-of-Frame Delimiter information to the data and appends the Frame Check Sequence at the end of the data. In half-duplex operation, the Tx MAC stores the first 64 bytes of data from the external FIFO in an internal buffer, to be used in re-transmitting data on collisions.  The SGMII Easy Connect configuration option adds pins and logic for seamless connection to the Lattice's Gigabit Ethernet PCS IP core.

Features

  • Compliant to IEEE 802.3z standard
  • Generic 8-bit host interface
  • 8-bit wide internal data path
  • Generic transmit and receive FIFO interface
  • Full-duplex operation in 1G mode
  • Full- and half-duplex operation in 10/100 mode
  • Transmit and receive statistics vector
  • Programmable Inter-Packet Gap (IPG)
  • Multicast address filtering
  • Selectable MAC operating options
    • Classic Tri-Speed MAC with G/MII
    • Gigabit MAC with GMII
    • SGMII Easy Connect MAC with GMII, configurable option available on LatticeECP3™, LatticeECP2/M, and LatticeSC/M devices
  • Supports
    • Full-duplex control using PAUSE frames
    • VLAN tagged frames
    • Automatic re-transmission on collision
    • Automatic padding of short frames
    • Multicast and Broadcast frames
    • Optional FCS transmission and reception
    • Optional MII management interface module
    • Jumbo frames up to 9600 bytes

Performance and Resource Utilization

Results for LatticeECP31
Configuration SLICEs  LUTs   REGs  EBRs External
Pins
fMAX (MHz)
 MIIM Module Operation Mode2
No Classic 1287 1870 1195 2 25 125
No GbE 1073 1500 1063 1 22 125
No SGMII 1279 1851 1175 2 4 125
Yes Classic 1437 2020 1347 2 27 125
Yes GbE 1233 1694 1215 1 24 125
Yes SGMII 1427 2016 1327 2 6 125

1. Performance and utilization characteristics are in Lattice ispLEVER 8.0 software targeting a LFE3-95E-6FN484CES FPGA. When using this IP core in a different density, speed, or grade within the LatticeECP3 family or in a different software version, performance may vary.

Results for LatticeECP2M1
Configuration SLICEs  LUTs   REGs  EBRs External
Pins
fMAX (MHz)
 MIIM Module Operation Mode2
No Classic  1385  1958  1201  2  25 125
No GbE  1141  1574  1063  1  22 125
No SGMII  1345  1922  1175  2  4 125
Yes Classic  1544  2125  1350  2  27 125
Yes GbE  1289  1709  1215  1  24 125
Yes SGMII  1511  2076  1327  2  6 125

1. Performance and utilization characteristics are in Lattice ispLEVER 8.0 software targeting a LFE2M35E-5F484CES device. When using this IP core in a different density, speed, or grade within the LatticeECP2M family or in a different software version, performance may vary.

Results for LatticeECP21
Configuration SLICEs  LUTs   REGs  EBRs External
Pins
fMAX (MHz)
 MIIM Module Operation Mode2
No Classic 1385 1958 1201  2  25 125
No GbE  1141  1574 1063  1  22 125
Yes Classic  1544  2125 1350  2  27 125
Yes GbE  1289  1709 1215  1  24 125

1. Performance and utilization characteristics are in Lattice ispLEVER 8.0 software targeting a LFE2-20E-5F484CES device. When using this IP core in a different density, speed, or grade within the LatticeECP2 family or in a different software version, performance may vary.
2.The SGMII Easy Connect option is only available on device families with SERDES I/O.

Results for LatticeEC/P1
Configuration SLICEs  LUTs   REGs  EBRs External
Pins
fMAX (MHz)
 MIIM Module Operation Mode2
No Classic 1370  1952  1205 2 25 125
No GbE  1166  1582  1094  1  22 125
Yes Classic  1529  2090  1358  2  27 125
Yes GbE  1330  1735  1248  1  24 125

1. Performance and utilization characteristics are in Lattice ispLEVER® 8.0 software and targeting a LFEC10E-5F484C device. When using this IP core in a different density, speed, or grade within the LatticeECP/EC family or in a different software version, performance may vary.
2.The SGMII Easy Connect option isþonly available on device families with SERDES I/O.

Results for LatticeSC/M1
Configuration SLICEs  LUTs   REGs  EBRs External
Pins
fMAX (MHz)
 MIIM Module Operation Mode2
No Classic 1340  1952 1198  2 25 125
No GbE  1095  1527  1064  1  22 125
No SGMII 1331 1937 1178 2 4 125
Yes Classic  1487  2134  1351  2  27 125
Yes GbE  1244  1738  1217  1  24 125
Yes SGMII 1473 2112 1339 2 6 125

1. Performance and utilization characteristics are in Lattice's ispLEVER 8.0 targeting a LFSC3GA15E-5F900CES device. When using this IP core in a different density, speed, or grade within the LatticeSC/M family or in a different software version, performance may vary.

Results for LatticeXP21
Configuration SLICEs  LUTs   REGs  EBRs External
Pins
fMAX (MHz)
 MIIM Module Operation Mode2
No Classic 1358  1958 1201  2 25 125
No GbE  1141  1574  1063  1  22 125
Yes Classic  1544  2125  1350  2  27 125
Yes GbE  1289  1709  1215  1  24 125

1. Performance and utilization characteristics are in Lattice ispLEVER 8.0 targeting a LFXP2-17E-6F484 device. When using this IP core in a different density, speed, or grade within the LatticeXP2 family or in a different software version, performance may vary.
2.The SGMII Easy Connect option isþonly available on device families with SERDES I/O.

Results for LatticeXP1
Configuration SLICEs  LUTs   REGs  EBRs External
Pins
fMAX (MHz)
 MIIM Module Operation Mode2
No Classic 1370  1952 1205  2  25 125
No GbE  1166  1582  1094  1  22 125
Yes Classic  1529  2090  1358  2  27 125
Yes GbE  1330  1735  1248  1  24 125

1. Performance and utilization characteristics are in Lattice ispLEVER 8.0 software targeting a LFXP10C-5F388CES device. When using this IP core in a different density, speed, or grade within the LatticeXP family or in a different software version, performance may vary.
2.The SGMII Easy Connect option isþonly available on device families with SERDES I/O.

Demo

A demo is available for the LatticeXP family and highlights the capability of the Tri-Speed Ethernet MAC IP core to function in a real network environment.   For more information about this demo, please click here.

Ordering Information

The Tri-Speed Ethernet MAC is a user-configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that the FPGA programming bitstream will have time-out logic unless a license for the IP is purchased.

Part Numbers:

LatticeECP3 TS-MAC-E3-U4
LatticeECP2M TS-MAC-PM-U4
LatticeECP2 TS-MAC-P2-U4
LatticeECP/EC TS-MAC-E2-U4
LatticeSC TS-MAC-SC-U4
LatticeXP2 TS-MAC-X2-U4
LatticeXP TS-MAC-XM-U4


IP Version: 3.1
Evaluate
: To download a full evaluation version of this IP, please go to the Lattice IP Server tab in the IPexpress Main Window.  All ispLeverCORE IP modules available for download are visible on this tab.
Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.