Tri-Speed Ethernet Media Access Controller

Overview

The Tri-Speed Ethernet Media Access Controller (TSMAC) core can be configured to operate in either the Gigabit mode (1000Mbits/sec data rate) or the Fast Ethernet mode (10/100 Mbits/sec data rate). Operation in either Gigabit mode or Fast Ethernet mode is selected by setting an internal register bit.

The Tri-Speed Ethernet MAC transmits and receives data between a host processor and an Ethernet network. The main function of the Ethernet MAC is to ensure that the Media Access rules specified in the 802.3 IEEE standard are met while transmitting a frame of data over Ethernet. On the receiving side, the Ethernet MAC extracts the different components of a frame and transfers them to higher applications through the FIFO interface.

The data received from the G/MII interface is first buffered until sufficient data is available to be processed by the Receive MAC (Rx MAC). The Preamble and the Start of Frame Delimiter (SFD) information are then extracted from the incoming frame to determine the start of a valid frame. The Receive MAC checks the address of the received packet and validates whether the frame can be received before transferring it into the FIFO. Only valid frames are transferred into the FIFO. This feature has the following two benefits: the systems need not re-calculate the Frame Check Sequence (FCS) again when the frame is being transmitted, and it also keeps the receive MAC relatively simple. The Tri-Speed MAC, however, always calculates CRC to check whether the frame was received error-free.

Features

• Compliant to IEEE 802.3z standard
• Generic 8-bit host interface
• 8-bit wide internal data path
• Generic transmit and receive FIFO interface
• Full-duplex operation in Gigabit mode
• Full- and half-duplex operation in 10/100 mode
• Transmit and receive statistics vector
• Programmable Inter Packet Gap (IPG)
• Multicast address filtering
• Supports
  • Full-duplex control using PAUSE frames
  • VLAN tagged frames
  • Automatic re-transmission on collision
  • Automatic padding of short frames
  • Multicast and Broadcast frames
  • Optional FCS transmission and reception
  • Optional MII management interface module
  • Jumbo frames up to 8192 bytes

The Tri-Speed Ethernet MAC is a user-configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may be prevented or the bitstream may have time logic present unless a license for the IP is purchased.

Performance and Resource Utilization¹

 ¹ Performance and utilization characteristics are in Lattice's ispLEVER® v.6.1 SP2 software. When using this IP core in a different density, speed, or grade within a Lattice FPGA family or in a different software version, performance may vary.

Demo

A demo is available for the LatticeXP family and highlights the capability of the Tri-Speed Ethernet MAC IP core to function in a real network environment.   For more information about this demo, please click here.

Ordering Information

Part Numbers:
For LatticeECP/EC: TS-MAC-E2-U3
For LatticeXP: TS-MAC-XM-U3
For LatticeXP2: TS-MAC-X2-U3
For LatticeECP2: TS-MAC-P2-U3
For LatticeSC: TS-MAC-SC-U3
For LatticeECP2M: TS-MAC-PM-U3

To download a full evaluation version of this IP, please go to the Lattice IP Server tab in the IPexpress Main Window. All ispLeverCORE IP modules available for download are visible on this tab.

To find out how to purchase the Tri-Speed Ethernet Media Access Controller IP Core, please contact your local Lattice Sales Office.

For information about evaluating or purchasing the Tri-Speed Ethernet Media Access Controller IP Core for the LatticeXP2 family, please contact your local Lattice Sales Office.