Serial Digital Interface (SDI) is the most popular raw video connectivity standard used in television broadcast studios and video production facilities. The availability of high-speed serial inputs/outputs and general purpose programmable logic makes FPGAs (field programmable gate arrays) ideal devices to be used for acquisition, mixing, storage, editing, processing and format conversion applications. Simpler applications use FPGAs to acquire SDI data from one or more SD (standard definition), HD (high definition) or 3G (3-Gigabit HD) sources, perform simple processing and re-transmit the video data in SDI format. Such applications require an SDI PHY (physical layer) interface and some basic processing blocks like a color space converter. In more complex applications, the acquired video is taken through multiple processing phases, like de-interlacing, video format conversion, filtering, scaling, graphics mixing and picture-in-picture display. FPGA devices can also be used as a bridge between SDI video sources and backplane protocols such as PCI Express or Ethernet, with or without any additional video processing.
Lattice's Tri-Rate SDI PHY IP (intellectual property) core is a complete SDI PHY interface that connects to the high-speed SDI serial data on one side (through LatticeECP3™ SERDES) and the formatted parallel video data on the other side. It enables faster development of applications for processing, storing, and bridging SDI video data. It is comprised of the following major functional blocks: SDI encoder/decoder, word alignment, CRC detection and checking, VPID (video payload identifier) insertion and extraction, and rate detection logic. The IP core supports the following interface standards and source formats for SDI as specified in standards published by the Society for Motion Picture and Television Engineers (SMPTE).
The IP, when connected with the LatticeECP3 SERDES, can transmit and/or receive any of the supported video standards and formats through a common physical serial interface. The IP core can automatically scan and lock on to any of the supported video streams. Receiving multiple standards requires appropriate external clocks to be supplied by the application in response to commands from the IP core.
| IP Express User Configurable Mode | SLICEs | LUTs | Registers | TxClock | RxClock |
|---|---|---|---|---|---|
| 1 - PHY function=Tx/Rx, Enable 3G level B=Yes, VPID insertion=On | 1306 | 2506 | 1795 | 181 | 150 |
| 2 - PHY function=Tx/Rx, Enable 3G level B=Yes, VPID insertion=Off | 918 | 1747 | 1283 | 248 | 176 |
| 3 - PHY function=Tx/Rx, Enable 3G level B=No, VPID insertion=On | 926 | 1772 | 1243 | 185 | 178 |
| 4 - PHY function=Tx/Rx, Enable 3G level B=No, VPID insertion=Off | 733 | 1403 | 1009 | 285 | 149 |
| 5 - PHY function=Tx, Enable 3G level B=Yes, VPID insertion=On | 436 | 845 | 491 | 182 | - |
| 6 - PHY function=Rx, Enable 3G level B=Yes | 905 | 1714 | 1321 | - | 164 |
1. Performance and utilization data are generated using an LFE3-95E-7FN1156CES device with Lattice Diamond 1.3 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family.
| Family | Part Number |
| LatticeECP3 | TR-SDI-PHY-E3-U1 |
IP Version: 1.3
Evaluate: To download a full evaluation version of this IP, go to the IPexpress tool and click the IP Server button in the toolbar. All LatticeCORE IP cores and modules available for download will be visible. For more information on viewing/downloading IP please read the IP Express Quick Start Guide.
Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.
© Lattice Semiconductor Corporation 2012
