Serial RapidIO 2.1 IP Core

Overview

The RapidIO Interconnect Architecture is an industry-standard, packet-based interconnect technology that provides a reliable, high-performance interconnect between NPUs (network processing units), CPUs (central processing units), and DSPs (digital signal processors). Serial RapidIO enables chip-to-chip, board-to-board, and system-to-system communications and is targeted at the networking, embedded, and storage markets.

RapidIO has won broad acceptance in wireless infrastructure applications, where it is used as a primary interconnect for DSP clusters in baseband processing.  In the past, vendors had to rely on expensive, premium FPGAs for these applications. However, the combination of the Serial RapidIO 2.1 IP core and Lattice's low-cost mid-range FPGA like the LatticeECP3 now allows customers to develop low-power infrastructure solutions for 3G, LTE and WiMAX without sacrificing performance or cost.

Serial RapidIO 1x Physical Layer Core Block Diagram

Features

• Serial RapidIO 2.1 endpoint core for processor bridging, control plane interfaces and bridging to legacy interface applications in a small footprint
• Allows for 1x, 2x, 4x lane configurations at 1.25Gbps
• Up to 3.125Gbps at 1x, 2x lane configurations
• Implements physical layer, transport layer, maintenance transaction handling and error management extensions.
• Provides infrastructure support for external logical layer functions, enabling maximum flexibility
• Provides a choice of logical layer functions that are important for the application
• Provides a choice of how logic layer functions interact with the rest of the system - SOC bus or streaming interfaces
• Supports software implementations of control plane oriented functions such as doorbells and messages
• Backward compatible with the v1.3 specification

Performance and Resource Utilization

1. Performance and utilization data are generated targeting an LFE3-70E-6N672 using Lattice ispLEVER 8.0 and Synplify Pro for Lattice C 2009.03L software. Performance might vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family.
2. f_MAX shown is for x1, x2, or x4 operation at 1.25Gbaud using -6 speed grade parts. Higher line rates may require faster speed grades. Please see section “Applications Information” on operating the core with line rates higher that 1.25Gbaud.

Ordering Information

IP Version: 1.0
Evaluate, Purchase: Unlike other IP from Lattice, the Serial RapidIO 2.1 IP cannot be directly downloaded from the Lattice IP Server with IPexpress tool.

Please request this IP from Lattice at lic_admn@latticesemi.com and include your name, company, and complete contact information. A setup file for installation of the IP into IPexpress will be sent to you. Execute the setup file and then use IPexpress for configuration of your IP. After successful evaluation, contact your local Lattice Sales Office to purchase the license.