SPI4 MACO Core

Overview

The LatticeSCM SPI4 MACO™ IP core implements an industry standard SPI4.2 interface used to transfer both variable length packets and fixed cell sizes between PHY and Link Layer devices in telecom and datacom applications. This flexibility makes it an attractive interface for Ethernet, SONET and ATM applications. Until now, this popular interface was only available as soft IP in FPGAs. The LatticeSCM device implements this core in an optimal combination of hard and soft gates to reduce the size of the core, reduce power and enhance user flexibility. Specifically, the Data Path is implemented in hard logic while the Status path is implemented in soft gates to enable designers to implement their own calendaring or prioritization schemes if they so choose.

This figure shows the SPI4 MACO Core implementation in the LatticeSCM

Note that the SPI4 IP Core is implemented using both MACO ASIC and soft logic in the FPGA array.  Since a significant portion of the implementation is in MACO, more of the FPGA Array is left for the user.

This figure shows the SPI4 MACO TX architecture.  See User Guide for RX architecture.

Features

• Fully compliant with OIF-SPI4.02.0 Specification
• Supports up to 256 logical ports
• 700 Mbps operation in Static Mode
• 1+ Gbps operation in Dynamic Mode
• Transmit/Receive Data Path
  • 16 bits wide, in-band port address, SOP, EOP indication, error control
  • LVDS I/O (IEEE 1596.3 – 1966 [1], ANSI/TIA/EIA-644-1995[2]
  • Source synchronous double edge clocking at 311MHz minimum
• Static and Dynamic Alignment Modes
  • Up to 1 Gbps Dynamic Phase Alignment
  • Up to 700 MHz Static Alignment
  • Additional Quarter Rate Mode for sub 10G traffic
• Transmit/Receive FIFO Status
  • 2 bit parallel FIFO status indication, in-band Start of FIFO status
  • LVTTL I/O or optional LVDS I/O (IEEE 1596.3)
  • Source synchronous clocking
• Various run-time user controls:
  • Individual receiver/transmitter resets
  • De-skew only reset, AIL only reset
  • Force idles (transmitter)
  • Enable/Disable Packing (transmitter)
  • Training Pattern (CAL_M, MAX_T) Programmable burst modes to support NPU requirements
• Link Layer Buffer Management Options (NEW):
  • Shared or per-channel buffer manager
  • Up to 16 separate physical FIFOs per Tx/Rx direction
  • Transmit Bandwidth Manager and Receive Channel Mapper
  • Parameterizable packet overflow and packet error drop
  • Graceful packet overflow drop
  • Both store & forward as well as cut-through operation
  • Parameterizable independent buffer depth per transmit and receive direction
  • Per channel empty, almost empty, full and almost full status
  • Programmable almost empty and almost full thresholds per channel
  • Dynamic channel provisioning
  • Programmable sequencer based scheduler. 
• Supported by System Bus and Serial Memory Interface (SMI) for in-circuit controllability
• Pre-engineered hard cores using MACO technology to conserve power, FPGA resources and designer time
• Multiple SPI4 IP core support per device
• Supported in Windows, Linux, or Unix based tool flows
• Supports both Verilog and VHDL tool flows

Software Requirements:

• ispLEVER version 7.0 or later
• MACO design kit
• MACO license file

To download this MACO IP, please go to the Lattice IP Server tab in the IPexpress Main Window. All ispLeverCORE IP modules available for download are visible on this tab.

Resource Utilization¹

1.Performance and utilization characteristics using Lattice ispLEVER 7.1 software. When using this IP core with different software or in a different speed grade, performance may vary. Performance and utilization characteristics have been verified on the latest version of Lattice ispLEVER software to be within ± 5% of the above numbers.

Buffer Manager Resource Utilization^{1, 2, 3}

1. Performance and utilization characteristics were obtained using Lattice ispLEVER 7.1 software. When using this IP core with different software, performance may vary. Performance and utilization characteristics have been verified on the latest version of Lattice ispLEVER software to be within ± 5% of the above numbers.
2. For cases where a multi-channel interleaved SPI4 line (configured via the GUI) is received into the SPI4 IP core, add ~1250 slices and ~1700 luts to the utilization numbers above.
3. The utilization numbers above were obtained through place and route of the “core only” design that is automatically created during IP core generation. For these cases, place and route was run using a -6 speed grade device and constraints consistent with a 16Gbps SPI4 line (500 MHz DDR). Depending line rate required and complexity of user logic functions, a slower speed grade (-5) may be used or a faster speed grade (-7) device may be required.

Licensing

All MACO IP is free of charge.  However a license key is required to enable simulation and bitstream generation. Please contact your local Lattice Sales Office to obtain your MACO IP license key.