SPI4.2

Overview

The SPI4 Intellectual Property (IP) core enables user instantiation of OIF-compliant System Packet Interface Level 4 Phase 2 Revision 1 (SPI4.2.1) cores in Lattice Field Programmable Gate Arrays (FPGAs).  The SPI4 IP core supports up to 256 data channels with aggregate throughputs of between 3 and 12.8Gbps and can be used to connect network processors with OC192 framers, mappers, and fabrics, as well as Gigabit and 10-Gigabit Ethernet MACs. This user's guide explains the functionality of the SPI4 core and how it can be applied to interconnect physical and link layer devices in 10Gbps POS, Ethernet, and ATM applications.  

• SPI4 core fully compliant with the OIF System Packet Interface Level 4 Phase 2 Revision 1 (SPI4.2.1) interface standard
• Supported through ispLEVER IPexpress for easy user configuration and parameterization
• Supports up to 256 independent channels 156-400MHz DDR Static timing mode operations. Supports non-standard “SPI4 Lite” line rates
• Supports both 64b and 128b internal architectures for optimization of either speed or size
• Requires only ~2000 slices (64b mode) for a full 256-channel Static mode core
• Supports full bandwidth utilization of the SPI4 line in both directions - requires no Idle cycles in the receive direction nor insertion of Idles in the transmit direction between bursts (as long as there is data available)
• Parity error checking/generation on all receive & transmit control & data words (DIP4) and status (DIP2) interfaces
• Parity error force capabilities on data (independent controls: control word and data) and status interfaces
• Various run-time user controls:
  • Force idles (transmitter)
  • Enable/Disable Packing (transmitter)
  • Training Pattern (CAL_M, MAX_T)
• Complete run-time programmability of all internal FIFO thresholds for efficient management of SPI4 line in terms of Lmax and packing
• Provides a direct interface to primary device I/O at the SPI4 interface and an internal FIFO interface to user logic
• Supports minimum transmit burst sizes in increments of 16 bytes from 16 bytes up to 1008 bytes for optimized Network Processor applications
• Support for packet sizes down to 4 bytes in length
• Fully configurable 512-location calendar RAM for Rx and Tx directions and associated 256-location status RAMs
• Two independently configurable methods of status reporting in the Receive and Transmit directions - RAM addressable and Transparent
• Rising or falling edge selectable Status Channel I/O independently configurable in the Receive and Transmit directionsXGMII interface to the PHY layer

The SPI4.2 is a user-configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may be prevented or the bitstream may have time logic present unless a license for the IP is purchased.

Performance and Resource Utilization

¹ Performance and utilization characteristics are in Lattice's ispLEVER® v7.0 software. When using this IP core in a different density, speed, or grade within the LatticeECP2M family or in a different software version, performance may vary.

¹ Performance and utilization characteristics are in Lattice's ispLEVER® v7.0 software. When using this IP core in a different density, speed, or grade within the LatticeSC/M family or in a different software version, performance may vary.

Ordering Information

Part Numbers:
For LatticeECP2: SPI-42-P2-U3
For LatticeECP2M: SPI-42-PM-U3
For LatticeSC/M: SPI-42-SC-U3

To download a full evaluation version of this IP, please go to the Lattice IP Server tab in the IPexpress Main Window. All ispLeverCORE IP modules available for download are visible on this tab. To find out how to purchase the SPI4.2 IP Core, please contact your local Lattice Sales Office.