Soft Error Detection

Overview

Soft errors occur when high-energy charged particles alter the stored charge in a memory cell in an electronic circuit. The phenomenon first became an issue in DRAM, requiring error detection and correction for large memory systems in high-reliability applications. As device geometries have continued to shrink, the probability of soft errors in SRAM is becoming significant for some systems. Designers are using a variety of approaches to minimize the effects of soft errors on system behavior.

SRAM-based FPGAs store logic configuration data in SRAM cells. As the number and density of SRAM cells in an FPGA increase, the probability that a soft error will alter the programmed logical behavior of the system increases. 

The Soft Error Detection Core utilizes a 17-bit CRC algorithm with the following attributes:

• 100% detection of single-bit errors
• 100% detection of two-bit errors within 10 adjacent frames
• 100% detection of multiple-bit errors within a 17-bit span
• (1-2^-17)*100% detection of random multiple-bit errors

The Soft Error Detection is a user-configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may be prevented or the bitstream may have time logic present unless a license for the IP is purchased.

¹ Performance and utilization characteristics are in Lattice's ispLEVER® v.5.1 SP2 software. When using this IP core in a different density, speed, or grade within the LatticeSC family or in a different software version, performance may vary.

Ordering Information

Part Numbers:
For LatticeSC: SED-CORE-SC-U1

To download a full evaluation version of this IP, please go to the Lattice IP Server tab in the IPexpress Main Window. All ispLeverCORE IP modules available for download are visible on this tab.

To find out how to purchase the Soft Error Detection IP Core, please contact your local Lattice Sales Office.