SGMII and Gb Ethernet PCS

A NEW VERSION OF THIS IP CORE IS AVAILABLE.  PLEASE VISIT SGMII-GBE PCS

Overview

The Lattice SGMII and Gb Ethernt PCS IP core implements the PCS functions of both the Cisco SGMII and the IEEE 802.3z (1000BaseX) specifications. The PCS mode is pin selectable. This IP core may be used in bridging applications and/or PHY implementations.

The Serial Gigabit Media Independent Interface (SGMII) is a connection bus for Ethernet Media Access Controllers (MACs) and Physical Layer Devices (PHYs) defined by Cisco Systems. It replaces the classic 22-wire GMII connection with a low pin count, 4-pair, differential SGMII connection. The classic GMII interface defined in the IEEE802.3 specification is strictly for Gigabit rate operation. However, the Cisco SGMII specification defines a method for operating 10 Mbps and 100 Mbps MACs over the interface. Moreover, the Cisco SGMII specification is comprised of more than just a bus interface definition; it defines a bridging function between SGMII and GMII buses.

These applications can be completely implemented in LatticeECP2M™ and LatticeSC™ Field Programmable Gate Array (FPGA) devices. As an example, Lattice has developed a reference design for a complete SGMII-to-(G)MII bridge. This reference design is included with the SGMII and Gb Ethernet PCS IP Core package and is described in detail in Appendix C.

IP Core usage

• Implements PCS functions of the CISCO SGMII Specification, Revision 1.7
• Implements PCS functions for 1000BASE-X
• Dynamically switches SGMII and 1000BASE-X PCS operation
• Supports Tri-Speed (G)MII - 1Gbps, 100Mbps, 10Mbps
• Pin selectable MAC/PHY mode for auto negotiation
• Provides parallel management interface port for control and status
• Includes Easy Connect option for seamless integration with Lattice's Tri-Speec MAC (TSMAC) IP core

The SGMII and Gb Ethernet PCS is a user-configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may be prevented or the bitstream may have time logic present unless a license for the IP is purchased.

Resource Utilization:

1) Performance and utilization characteristics are using Lattice’s ispLEVER v7.1 software and Synplify v9.4L synthesis with an LFSC3GA25E, -5, 1020FPBGA.  When using this IP core in a different density, speed, or grade or in a different software version, performance may vary.

2) The SGMII requires operation at 125 MHz, therefore a higher frequency is not stated. However this core can easily attain frequencies above 200 MHz in a LatticeSC speed-grade 5 device.

1) Performance and utilization characteristics are using Lattice’s ispLEVER v7.1 software and Synplify v9.4L synthesis with an ECP2M35E-5F672.  When using this IP core in a different density, speed, or grade or in a different software version, performance may vary.

2) The SGMII requires operation at 125 MHz, therefore a higher frequency is not stated. However this core can easily attain frequencies above 140 MHz in a LatticeECP2M speed-grade 5 device.

Ordering Information

Part Numbers:
For LatticeSC: SGMII-SC-U3
For LatticeECP2M: SGMII-PM-U3

To download a full evaluation version of this IP, please go to the Lattice IP Server tab in the IPexpress Main Window. All ispLeverCORE IP modules available for download are visible on this tab.

To find out how to purchase the SGMII and Gb Ethernet PCS IP Core, please contact your local Lattice Sales Office.