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SGMII PCS

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Overview

IPexpress User Configurable Logo The Serial Gigabit Media Independent Interface (SGMII) is a connection bus for Ethernet Media Access Controllers (MACs) and Physical Layer Devices (PHYs) defined by Cisco Systems. It replaces the classic 22-wire GMII connection with a low pin count, 4-pair, differential SGMII connection. The classic GMII interface defined in the IEEE802.3 specification is strictly for Gigabit rate operation. However, the Cisco SGMII specification defines a method for operating 10 Mbps and 100 Mbps MACs over the interface. Moreover, the Cisco SGMII specification is comprised of more than just a bus interface definition; it defines a bridging function between SGMII and GMII buses.

The Lattice SGMII PCS IP core implements the PCS functions of the Cisco SGMII specification. Users may use this IP core in their own SGMII-to-GMII bridging applications. The entire SGMII bridging function can be implemented in Lattice Field Programmable Gate Array (FPGA) devices.  

 SGMII PCS IP Core Block Diagram

Features
  • Supports PCS functions of the Cisco SGMII Specification, Revision 1.7
  • 8-bit GMII Interface operating at 125 MHz
  • 8-bit Code-Group Interface operating at 125 MHz
  • Pin selectable MAC/PHY mode for auto negotiation
  • Management Interface Port for control and maintenance

 

The SGMII PCS is a user-configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may be prevented or the bitstream may have time logic present unless a license for the IP is purchased.

 

Performance and Resource Utilization

Results for LatticeSC1
SLICEs LUTs Registers I/Os3 fMAX2
419 561 553 89 125 MHz
1 Performance and utilization characteristics are in Lattice’s ispLEVER 6.1 software with Synplify synthesis.  When using this IP core in a different density, speed, or grade within the LatticeSC family or in a different software version, performance may vary. 
2 The SGMII requires operation at 125 MHz, therefore a higher frequency is not stated. However this core can easily attain frequencies above 200 MHz in a LatticeSC speed-grade 5 device.  Please consult the static timing report in your actual application for the actual maximum in that context.
3 I/Os are for core-only top-level instantiation. The actual core does not actually require any primary I/O other than SERDES interface.

 

Results for LatticeECP2M1
SLICEs LUTs Registers I/Os3 fMAX2
586 733 689 89 125 MHz
1 Performance and utilization characteristics are in Lattice’s ispLEVER 6.1 software with Synplify synthesis.  When using this IP core in a different density, speed, or grade within the LatticeECP2M family or in a different software version, performance may vary.
2 The SGMII requires operation at 125 MHz, therefore a higher frequency is not stated. However this core can easily attain frequencies above 140 MHz in a LatticeECP2M speed-grade 5 device. Please consult the static timing report in your actual application for the actual maximum in that context.
3 I/Os are for core-only top-level instantiation. The actual core does not actually require any primary I/O other than SERDES interface.

 

Ordering Information

Part Numbers:
For LatticeSC: SGMII-SC-U2
For LatticeECP2M: SGMII-PM-U2

 

To download a full evaluation version of this IP, please go to the Lattice IP Server tab in the IPexpress Main Window. All ispLeverCORE IP modules available for download are visible on this tab.

To find out how to purchase the SGMII PCS IP Core, please contact your local Lattice Sales Office.