RLDRAM Controller MACO Core

Overview

The Reduced Latency Dynamic Random Access Memory (RLDRAM) Controller is a general-purpose memory controller that interfaces with industry standard RLDRAM. The controller can be configured to function as RLDRAM I, RLDRAM II CIO (Common I/O) or RLDRAM II SIO (Separate I/O). The RLDRAM is a high-speed memory device used mainly in high bandwidth, latency sensitive application like communications, data storage etc. Data is transferred on both edges of the clock, doubling the rate of data transfer. This IP provides an interface between the RLDRAM and the generic bus interface.

The RLDRAM controller is designed to support RLDRAM I with target speeds up to 300 MHz DDR and RLDRAM II CIO or SIO modes with target speeds up to 400 MHz DDR.

RLDRAM Controller block diagram:

Detail diagram including the MACO physical partitioning:

Note the RLDRAM IP Core is implemented using both MACO ASIC gates and soft logic in the FPGA array. Since a significant portion of the implementation is in MACO, more of the FPGA Array is left for the user.

Features:

• Controller operates at half the memory clock frequency
• Allows programmable burst lengths of
  • 2 or 4 in RLDRAM I mode
  • 2, 4 or 8 in RLDRAM II mode
• Includes a reconfigurable refresh counter
• Command & Write Data pipeline to maximize throughput
• Supports the following commands at the user interface:
  • READ
  • WRITE
  • LOAD_MR
• Contains command pipeline to maximize throughput
• Supports:
  • Data path widths of 16 and 32 bits in RLDRAM I mode
  • Data path widths of 9, 18, 36 and 72 bits in RLDRAM II SIO mode (& 144 in CIO mode)
  • Data Mask signals
• Supports up to 8 chip selects in RLDRAM II SIO and CIO modes
• Generates differential output clocks (CK,CK#)
• Accepts differential input data clocks (DK,DK#)
• Supports RLDRAM II CIO MiniDIMM_72 and MiniDIMM_144, and RLDRAM II SIO MiniDIMM_72
• Includes DLL to align DQ and QK transitions with CK
• Supports user-selectable 1, 2, 4 and 8 DLLs for the 72 and 144 bit mini-DIMMs

 

Software Requirements:

• ispLEVER version 7.0 or later
• MACO design kit
• MACO license file

To download this MACO IP, please go to the Lattice IP Server tab in the IPexpress Main Window. All ispLeverCORE IP modules available for download are visible on this tab.

 

Resource Utilization:¹

Results for LatticeSCM

Configuration				SLICEs	LUTs	REGs	PIOs
Type	Data Width	Address Width	Mem Speed (MHz)
RLDRAM I	32	20	200	490	416	763	371
RLDRAM I	16	21	200	254	216	409	229
RLDRAM II CIO	72	21	400	882	902	1,513	750
RLDRAM II CIO	18	21	400	266	240	418	249
RLDRAM II SIO	72	21	400	882	906	1,513	822
RLDRAM II SIO	18	21	400	266	240	418	267

1) Performance and utilization characteristics are generated using Lattice's ispLEVER^® v7.1 software and Synplify Pro v9.4. When using this IP core with different software, results may vary.  Not all configurations will fit on smaller LatticeSCM devices.

 

Licensing

All MACO IP is free of charge.  However a license key is required to enable simulation and bitstream generation. Please contact your local Lattice Sales Office to obtain your MACO IP license key.