Quad SPI-3 to SPI-4 PHY Layer Bridge

Overview

The Quad SPI-3 to SPI-4 Bridge Intellectual Property (IP) Core targets the programmable array section of the ORCA ORSPI4 FPSC and provides the PHY Layer bridging function between one to four SPI-3 links and a SPI-4 link.

Features

• Complete Quad SPI-3 to SPI-4 PHY Layer Bridge Solution Based on the ORCA ORSPI4 FPSC
• IP Targeted to the ORSPI4 Programmable Array Section Implements Functionality Conforming to OIF-SPI3-01.0, Including:
  • Up to four full featured SPI-3 PHY Interfaces
  • Up to eight ports supported per Interface
  • Parameterizable FIFO size selection
  • Parameterizable Byte or Packet Mode selection
  • Configurable through the MicroProcessor Interface (MPI) ORCA 4 System Bus
  • Programmable parity type on SPI-3 bus
• SPI-4 Functionality Supported by the Embedded Section of the ORSPI4, Including:
  • Standard 10 Gbps physical to link layer interface
  • Support for "static" and "dynamic" alignment at the receive interface
  • Single-link and multi-link operation
  • SPI-4.2 transmit data protocol support logic
  • Embedded calender-based sequence port polling mechanism and bandwidth allocation for 256 ports

Evaluation Configurations

¹ Performance and utilization characteristics are generated using an ORSPI4-2FE1036C in Lattice’s ispLEVER v.4.0 software. When using this IP core in a different density, package, speed, or grade within the ORCA 4 family, performance may vary.

Ordering Information

Part Numbers:
For ORCA FPSC: SPI-324P-O4-N1

To find out how to purchase the Quad SPI-3 to SPI-4 PHY Layer Bridge IP Core, please contact your local Lattice Sales Office.