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QDRII+ SRAM Controller MACO Core

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Overview

The second generation Quad-Data-Rate (QDRII) Static Random Access Memory (SRAM) Controller is a general purpose memory controller that interfaces with industry standard QDRII and QDRII+ SRAM. The controller can be configured to function in two-word burst or four-word burst modes. It can also be configured to have an 18-bit bus or a 36-bit data bus. The data is transferred on both edges of the clock, doubling the rate of data transfer. Separate read and write data buses again double the data rate.

The QDRII+ IP Core is implemented using both MACO ASIC gates and soft logic in the FPGA array.  Since a significant portion of the implementation is in MACO, more of the FPGA Array is left for the user.

IPexpress User Configurable Logo
LatticeSC Maco Logo

Block Diagram:

 

QDRII/II+ SRAM Controller MACO Core

 

Features:

  

Software Requirements:

To download this MACO IP, please go to the Lattice IP Server tab in the IPexpress Main Window. All ispLeverCORE IP modules available for download are visible on this tab.

 

Resource Utilization:1

Results for LatticeSCM
Configuration SLICEs  LUTs   Regs   PIOs 
Type Data Width Address Width Mem Speed2
(MHz)
R/W FIFO Depth Latency Burst Mode

QDRII+

18

18

3002

4 / 4

2.5

4

230

297

233

194

QDRII+

36

18

3002

4 / 4

2.0

4

342

406

382

194

QDRII

18

18

2502

64 / 64

1.5

2

453

717

242

194

1) Performance and utilization characteristics are generated using Lattice's ispLEVER® v7.0 software. When using this IP core with different software or in a different speed grade, performance may vary.  Not all configurations will fit on smaller LatticeSCM devices. These results are from Synplify v8.8L2.

2) Performance results for -5 speed grade.

 

Licensing

All MACO IP is free of charge.  However a license key is required to enable simulation and bitstream generation. Please contact your local Lattice Sales Office to obtain your MACO IP license key. 

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