PCS Pipe IP Core

Documents & Downloads

Intel defined the PHY Interface for PCI Express (PIPE) as a standard interface between a PHY device and the Media Access (MAC) layer for PCI Express (PCIe) applications. The PIPE interface allows the PCI Express PHY device and the MAC layer to be implemented in discrete form (using an off-the-shelf PHY device) or in integrated form. The partitioning of the PCI Express Physical Layer shown below illustrates this flexibility.
PCS Pipe - PHY Layer Partitioning

The Lattice PCS PIPE IP core offers PCI Express PHY device functionality, compliant to the Intel PIPE Architecture Draft Version 1.00 (PIPE Ver 1.00), to any endpoint solutions. The PCS PIPE IP core utilizes the SERDES/PCS integrated in LatticeECP3 and LatticeECP2M FPGAs. The Lattice PCS PIPE IP core can be configured to support a link with one or four lanes.

General Features

LatticeECP3 PCS PIPE IP core (v4.1)
PIPE Selection Fully compliant to PIPE Rev 1.00 specification Standard PCI Express PHY interface allows for multiple IP sources Selectable 8-bit or 16-bit interface to transmit and receive PCI Express data Holding registers/FIFO for staging transmit and receive data Multiple x1 channel support SERDES/PCS Selection Selectable SERDES quad location for LatticeECP3 devices Selectable x1, multiple x1or x4 PCI Express implementations Selectable SERDES channel for PCI Express x1 mode Clock/data recovery from the serial stream Direct disparity control for use in transmitting compliance pattern 8b10b encoder/decoder and error indication Receiver detection 2.5GT/s full-duplex rate per channel

LatticeECP3 PCS PIPE IP core (v4.1)

PIPE Selection

Fully compliant to PIPE Rev 1.00 specification
Standard PCI Express PHY interface allows for multiple IP sources
Selectable 8-bit or 16-bit interface to transmit and receive PCI Express data
Holding registers/FIFO for staging transmit and receive data
Multiple x1 channel support

SERDES/PCS Selection

Selectable SERDES quad location for LatticeECP3 devices
Selectable x1, multiple x1or x4 PCI Express implementations
Selectable SERDES channel for PCI Express x1 mode
Clock/data recovery from the serial stream
Direct disparity control for use in transmitting compliance pattern
8b10b encoder/decoder and error indication
Receiver detection
2.5GT/s full-duplex rate per channel

LatticeECP2M PCS PIPE IP core (v3.3)
PIPE Section Fully compliant to PIPE Ver_1.00 Standard PCI Express PHY interface allows for multiple IP sources Selectable 8-bit or 16-bit interface to transmit and receive PCI Express data Holding registers/FIFOs for staging transmit and receive data SERDES/PCS Section Selectable SERDES Quad location for LatticeECP2M50 and larger devices Selectable x1or x4 PCI Express implementations Selectable SERDES Channel for PCI Express x1 mode Clock/data recovery from the serial stream Direct disparity control for use in transmitting compliance pattern 8b10b encoder/decoder and error indication Receiver detection 2.5GT/s full-duplex rate per channel

LatticeECP2M PCS PIPE IP core (v3.3)

PIPE Section

Fully compliant to PIPE Ver_1.00
Standard PCI Express PHY interface allows for multiple IP sources
Selectable 8-bit or 16-bit interface to transmit and receive PCI Express data
Holding registers/FIFOs for staging transmit and receive data

SERDES/PCS Section

Selectable SERDES Quad location for LatticeECP2M50 and larger devices
Selectable x1or x4 PCI Express implementations
Selectable SERDES Channel for PCI Express x1 mode
Clock/data recovery from the serial stream
Direct disparity control for use in transmitting compliance pattern
8b10b encoder/decoder and error indication
Receiver detection
2.5GT/s full-duplex rate per channel

Performance and Resource Utilization

LatticeECP3¹
Configuration	Data Width	Active Channels	Quad	SLICEs	LUTs	Registers	EBRs	f_MAX (MHz)
x1	8	0	PCSB	117	105	172	-	263
x1	16	0	PCSB	132	125	192	-	177
x4	8	0-3	PCSB	312	315	475	-	256
x4	16	0-3	PCSB	395	491	558	-	155

1.Performance and utilization data are targeting an LFE-95E-7FN672CES device using Diamond 1.0 and Synplify Pro D-2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family.

Ordering Information

IP Version: LatticeECP3: 4.1 and LatticeECP2M: 3.3
Evaluate: To download a full evaluation version of this IP, please go to the Lattice IP Server tab in the IPexpress Main Window. All LatticeCORE IP modules available for download are visible on this tab.
Purchase: The Lattice PCS PIPE IP core is available for free to PCI Express IP core licensees.