Intel defined the PHY Interface for PCI Express (PIPE) as a standard interface between a PHY device and the Media Access (MAC) layer for PCI Express (PCIe) applications. The PIPE interface allows the PCI Express PHY device and the MAC layer to be implemented in discrete form (using an off-the-shelf PHY device) or in integrated form. The partitioning of the PCI Express Physical Layer shown below illustrates this flexibility.
The Lattice PCS PIPE IP core offers PCI Express PHY device functionality, compliant to the Intel PIPE Architecture Draft Version 1.00 (PIPE Ver 1.00), to any endpoint solutions. The PCS PIPE IP core utilizes the SERDES/PCS integrated in LatticeECP3 and LatticeECP2M FPGAs. The Lattice PCS PIPE IP core can be configured to support a link with one or four lanes.
|LatticeECP3 PCS PIPE IP core (v4.1)|
|LatticeECP2M PCS PIPE IP core (v3.3)|
|Configuration||Data Width||Active Channels||Quad||SLICEs||LUTs||Registers||EBRs||fMAX (MHz)|
1.Performance and utilization data are targeting an LFE-95E-7FN672CES device using Diamond 1.0 and Synplify Pro D-2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family.
IP Version: LatticeECP3: 4.1 and LatticeECP2M: 3.3
Evaluate: To download a full evaluation version of this IP, please go to the Lattice IP Server tab in the IPexpress Main Window. All LatticeCORE IP modules available for download are visible on this tab.
Purchase: The Lattice PCS PIPE IP core is available for free to PCI Express IP core licensees.