LatticeMico32 Architecture

The LatticeMico32™ is a highly configurable 32-bit Harvard architecture “soft” microprocessor core for Lattice FPGA devices. By combining a 32-bit wide instruction set with 32 general purpose registers, the LatticeMico32 provides the performance and flexibility suitable for a wide variety of markets. Using a RISC architecture, the core consumes minimal device resources, while maintaining the performance required for a broad application set.  To accelerate the development of microprocessor systems, several optional WISHBONE compatible peripheral components may be integrated with the LatticeMico32.

Key Features and Benefits

• Optimized for Lattice FPGA Devices
• Performance Enhanced Feature Set
  • RISC architecture
  • 32-bit data path and 32-bit instructions
  • 32 general purpose registers
  • Handles up to 32 external interrupts
  • Optional instruction and data caches
  • Dual WISHBONE memory interfaces (Instruction and Data)

LatticeMico32 Processor Block Diagram
[Click to see full-size version]

Three Configurations to Optimize Area and Performance

• Basic 
  • No Multiplier
  • Multicycle Shifter
  • No Cache
• Standard
  • Multiplier
  • Pipelined Shifter
  • 8K I-Cache, No D-Cache
• Full
  • Multiplier
  • Pipelined Shifter
  • 8K I-Cache, 8K D-Cache

Performance and utilization characteristics are generated using Lattice's ispLEVER® 6.1 software. When using the LatticeMico32 in a different density, speed, or grade within the LatticeECP2/M family, performance may vary.

For information about the LatticeMico32 for the LatticeSC/M and LatticeXP families, please contact your local Lattice Sales Office.

Looking for an 8-bit microcontroller?  Check out the LatticeMico8.