Interleaver/De-Interleaver

Overview

Interleaving is a technique commonly used in communication systems to overcome correlated channel noise such as burst error or fading. The interleaver rearranges input data such that consecutive data are split among different blocks. At the receiver end, the interleaved data is arranged back into the original sequence by the de-interleaver. As a result of interleaving, correlated noise introduced in the transmission channel appears to be statistically independent at the receiver and thus allows better error correction.  

The Lattice Interleaver/De-interleaver IP Core supports rectangular block type and convolutional architectures. Rectangular interleaving arranges the input data row-wise in a matrix. The interleaved data is obtained by reading the columns of the matrix. Convolutional interleaving feeds the input data to a number of branches, each of which has a shift register with pre-defined length. The output data is taken from the branch outputs. Lattice's Convolutional Interleaver/De-interleaver IP Cores are compliant with ATSC and DVB standards, while the Rectangular Interleaver/De-interleaver is compliant with IEEE 802.16a standard.

Features

• High Performance and Area Efficient Symbol Interleaver/De-interleaver
• Supports Multiple Standards, Such as DVB, ATSC and IEEE 802.16
• Convolutional and Rectangular Block Type Architectures Available
• Fully Synchronous Design Using a Single Clock
• Symbol Size from 1 to 256 Bits
• Full Handshake Capability for Input and Output Interfaces
• Rectangular Block Type Features
  • Variable block size
  • Variable number of rows
  • Variable number of columns
  • Row permutations
  • Column permutations
• Convolutional Type Features
  • User-configurable number of branches
  • User-configurable branch length

Performance and Resource Utilization

¹ Performance and utilization characteristics are generated using LFEC20E-5F672C in Lattice’s ispLEVER 7.1 software. When using this IP core in a different density, speed, or grade within the LatticeECP/EC family, performance may vary.

¹ Performance and utilization characteristics are generated using LFE2-50E-7F672C in Lattice’s ispLEVER 7.1 software. When using this IP core in a different density, speed, or grade within the LatticeECP2 family, performance may vary.

¹ Performance and utilization characteristics are generated using LFE2M-35E-7F672C in Lattice’s ispLEVER 7.1 software. When using this IP core in a different density, speed, or grade within the LatticeECP2M family, performance may vary.

¹ Performance and utilization characteristics are generated using LFSC3GA25E-7F900C in Lattice’s ispLEVER 7.1 software. When using this IP core in a different density, speed, or grade within the LatticeECP2 family, performance may vary. 

¹ Performance and utilization characteristics are generated using LFXP20E-5F484C in Lattice’s ispLEVER 7.1 software. When using this IP core in a different density, speed, or grade within the LatticeXP family, performance may vary.

¹ Performance and utilization characteristics are generated using LFXP2-17E-7F256C in Lattice’s ispLEVER 7.1 software. When using this IP core in a different density, speed, or grade within the LatticeXP2 family, performance may vary.

¹ Performance and utilization characteristics are generated using LFX125B-04F256C in Lattice’s ispLEVER 7.1 software. The evaluation version of this IP core only works on this specific device density, package and speed grade.
² Programmable Function Unit (PFU) is a standard logic block of Lattice FPGA devices. For more information, see the data sheet of the device.

Ordering Information

Part Numbers:
For ispXPGA:  INTV-DINT-XP-N1
For LatticeECP/EC:  INTV-DINT-E2-U3
For LatticeECP2:  INTV-DINT-P2-U3
For LatticeECP2M:  INTV-DINT-PM-U3
For LatticeSC:  INTV-DINT-SC-U3
For LatticeXP:  INTV-DINT-XM-U3
For LatticeXP2:  INTV-DINT-X2-U3

To find out how to purchase the Interleaver/De-Interleaver IP Core, please contact your local Lattice Sales Office.