Interleaver/De-Interleaver

Overview

Interleaving is a technique commonly used in communication systems to overcome correlated channel noise such as burst error or fading. The interleaver rearranges input data such that consecutive data are spaced apart. At the receiver end, the interleaved data is arranged back into the original sequence by the de-interleaver. As a result of interleaving, correlated noise introduced in the transmission channel appears to be statistically independent at the receiver and thus allows better error correction.

The Lattice Interleaver/de-interleaver IP core supports rectangular block type and convolutional architectures. Rectangular interleaving arranges the input data row-wise in a matrix. The interleaved data is obtained by reading the columns of the matrix. Convolutional interleaving feeds the input data to a number of branches, each of which has a shift register with pre-defined length. The output data is taken from the branch outputs. Lattice’s Convolutional Interleaver/de-interleaver IP Cores are compliant with ATSC and DVB standards, while the Rectangular Interleaver/de-interleaver is compliant with IEEE 802.16a standard.

Features

• High Performance and Area Efficient Symbol Interleaver/De-interleaver
• Supports Multiple Standards, Such as DVB, ATSC and IEEE 802.16
• Convolutional and Rectangular Block Type Architectures Available
• Fully Synchronous Design Using a Single Clock
• Symbol Size from 1 to 256 Bits
• Full Handshake Capability for Input and Output Interfaces
• Rectangular Block Type Features
  • Variable block size
  • Variable number of rows
  • Variable number of columns
  • Row permutations
  • Column permutations
• Convolutional Type Features
  • User-configurable number of branches
  • User-configurable branch length

Performance and Resource Utilization

1. Performance and utilization data are generated using an LFE2M-35E-7F672C device with Lattice’s ispLEVER 7.1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2M family. 

1. Performance and utilization data are generated using an LFE2-50E-7F672C device with Lattice’s ispLEVER 7.1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2 family.

1. Performance and utilization data are generated using an LFEC20E-5F672C device with Lattice’s ispLEVER 7.1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP/EC family.

1. Performance and utilization data are generated using an LFSC3GA25E-7F900C device with Lattice’s ispLEVER 7.1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeSC/M families.

1. Performance and utilization data are generated using an LFXP2-17E-7F256C device with Lattice’s spLEVER 7.1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeXP2 family.

1. Performance and utilization data are generated using an LFXP20C-5F484C device with Lattice’s ispLEVER 7.1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeXP family.

Ordering Information

IP Version: 3.3
Evaluate: To download a full evaluation version of this IP, please go to the Lattice IP Server tab in the IPexpress Main Window.  All ispLeverCORE IP modules available for download are visible on this tab. 
Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.