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FIR Filter Generator

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Overview

IPexpress User Configurable LogoA Finite Impulse Response (FIR) filter performs a convolution of an input data sequence with the filter's impulse response (the discrete-time inverse Fourier transform of its desired frequency response), which is stored in memory. The equation for performing the convolution is given by
FIR Filter Formula

where yn is the filter output at sample n, xn-i is the value of the filter input i samples in the past, and hi is the ith value of the filter impulse response.


The Lattice FIR (Finite Impulse Response) Filter IP core is a widely configurable, multi-channel FIR filter, implemented using high performance sysDSP™ blocks available in Lattice devices. In addition to single rate filters, the IP core also supports a range of polyphase decimation and interpolation filters.  The utilization versus throughput trade-off can be controlled by specifying the number of multipliers used for implementing the filter.  The FIR Filter IP core supports as high as 256 channels, with each having up to 2048 taps.  The input data, coefficient and output data widths are configurable over a wide range.  The IP core uses full internal precision while allowing variable output precision with several choices for saturation and rounding.  The coefficients of the filter can be specified at generation time and/or re-loadable during run-time through input ports.


Functional Block Diagram of the FIR Filter IP Core

Fir Filter Block Diagram

Features

  • Variable number of taps up to 2048
  • Input and coefficients widths of 4 to 32 bits
  • Multi-channel support for up to 256 channels
  • Decimation and Interpolation ratios from 2 to 256
  • Support for half-band filter
  • Configurable parallelism from fully parallel to serial
  • Signed or unsigned data and coefficients
  • Coefficients symmetry and negative symmetry optimization
  • Re-loadable coefficients support
  • Full precision arithmetic
  • Selectable output width and precision
  • Selectable overflow: wrap-around or saturation
  • Selectable rounding: truncation, round towards zero, round away from zero, round to nearest and convergent rounding
  • Width and precision specified using fixed point notations
  • Handshake signals to facilitate smooth interfacing

Performance and Resource Utilization

 
LatticeECP31
Mode   SLICEs  LUTs  Registers  sysDSP blocks  sysMEM EBRs fMAX (MHz) 
4 channels, 64 taps, 1 multiplier  97 87 188 1 2 340
1 channel, 32 taps, 32 multipliers  448 804 636 16 - 347
1 channel, 32 taps, 8 multiplies 408 498 687 5 - 393
1. Performance and utilization characteristics are generated targeting LFE3-70E-8FN672CES using Lattice ispLEVER 7.2 SP1 and Synplify Pro 9.6L2 software.  When using this IP core in a different density, speed, or grade within the LatticeECP3 family or in a different software version, performance may vary.
 
LatticeECP2M1
Mode   SLICEs  LUTs  Registers  sysDSP blocks  sysMEM EBRs fMAX (MHz) 
4 channels, 64 taps, 1 multiplier 122 122 242 1 2 370
1 channel, 32 taps, 32 multipliers  415 268 806 8 - 298
1 channel, 32 taps, 8 multiplies 378 530 622 2 - 324
1. Performance and utilization characteristics are generated targeting LFE2M50E-7F672C using Lattice ispLEVER 7.2 SP1 and Synplify Pro 9.6L2 software. When using this IP core in a different density, speed, or grade within the LatticeECP2M/S family or in a different software version, performance may vary.
  
LatticeECP21
Mode   SLICEs  LUTs  Registers  sysDSP blocks  sysMEM EBRs fMAX (MHz) 
4 channels, 64 taps, 1 multiplier  122 122 242 1 2 370
1 channel, 32 taps, 32 multipliers  415 268 806 8 - 294
1 channel, 32 taps, 8 multiplies 378 530 622 2 - 325
1. Performance and utilization characteristics are generated targeting LFE2-50E-7F672C using Lattice ispLEVER 7.2 SP1 and Synplify Pro 9.6L2 software. When using this IP core in a different density, speed, or grade within the LatticeECP2/S family or in a different software version, performance may vary.
LatticeECP1
Mode   SLICEs  LUTs  Registers  sysDSP blocks  sysMEM EBRs fMAX (MHz) 
4 channels, 64 taps, 1 multiplier  130 115 242 1 2 237
1 channel, 32 taps, 32 multipliers  413 264 806 8 - 172
1 channel, 32 taps, 8 multiplies 443 655 622 2 - 172
1. Performance and utilization characteristics are generated targeting LFECP33E-5F672C using Lattice ispLEVER 7.2 SP1 and Synplify Pro 9.6L2 software. When using this IP core in a different density, speed, or grade within the LatticeECP family or in a different software version, performance may vary.  
LatticeXP21
Mode   SLICEs  LUTs  Registers  sysDSP blocks  sysMEM EBRs fMAX (MHz) 
4 channels, 64 taps, 1 multiplier  122 122 242 1 2 314
1 channel, 32 taps, 32 multipliers  415 268 806 8 - 292
1 channel, 32 taps, 8 multiplies 378 530 622 2 - 292
1. Performance and utilization characteristics are generated targeting LFXP2-40E-7F672C using Lattice ispLEVER 7.2 SP1 and Synplify Pro 9.6L2 software. When using this IP core in a different density, speed, or grade within the LatticeXP2 family or in a different software version, performance may vary.

Ordering Information

Family Part Numbers
LatticeECP3 FIR-COMP-E3-U4
LatticeECP2M FIR-COMP-PM-U4
LatticeECP2 FIR-COMP-P2-U4
LatticeECP FIR-COMP-E2-U4
LatticeXP2 FIR-COMP-X2-U4

IP Express Version: 4.1
Evaluate: To download a full evaluation version of this IP, please go to the Lattice IP Server tab in the IPexpress Main Window. All ispLeverCORE IP modules available for download are visible on this tab.
Purchase: To find out how to purchase the FIR Filter Generator IP Core, please contact your local Lattice Sales Office.