DDR SDRAM Controller - Pipelined

Overview

The Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller that interfaces with industry standard DDR SDRAM. The memory controller provides a generic command interface to the user's application. This interface reduces the effort to integrate the module with the remainder of the application and minimizes the need to deal with the DDR SDRAM command interface. The timing parameters for the memory can be set through the signals that are input to the core as part of the configuration interface. This enables switching between different memory devices and modification of timing parameters to suit the application using the same netlist.

Features

• Interfaces to Industry Standard DDR SDRAM
• High-Performance DDR 400/333/266/200/133 operation for LatticeSC, LatticeECP2, and LatticeECP2M devices and DDR 333/266/200/133 operation for LatticeXP and LatticeECP/EC devices
• Programmable Burst Lengths of 2, 4 or 8
• Programmable CAS Latency of 2 or 3 Cycles
• Intelligent Bank Management to Minimize ACTIVE Commands
• Supports All Standard DDR Commands
• Synchronous Implementation for Reliable Operation
• Command Pipeline to Maximize Throughput
• Support for Two DIMM
• Supports all Common Memory Configurations
  • SDRAM data path widths of 8, 16, 32, 64 and 72 bits
  • Variable address widths for different memory devices
  • Programmable timing parameters
  • Byte level writing through Data Mask signals
  • Chip selects of 1, 2, 4 or 8 bits
  • Burst termination

The DDR SDRAM Controller - Pipelined is available as an IPexpress user configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may be prevented or the bitstream may have time logic present unless a license for the IP is purchased.

Performance and Utilization

¹Using parameter defaults from Table 1 of the User Guide.  Performance and utilization characteristics are generated using LFXP20E-5F484C in Lattice's ispLEVER 7.0 SP1 software. When using this IP core with different parameters, density, or speed grade within the LatticeXP family, performance may vary. 

¹Using parameter defaults from Table 1 of the User Guide.  Performance and utilization characteristics are generated using LFXP2-17E-7F484C in Lattice's ispLEVER 7.0 SP1 software. When using this IP core with different parameters, density, or speed grade within the LatticeXP2 family, performance may vary.

¹Using parameter defaults from Table 1 of the User Guide.  Performance and utilization characteristics are generated using LFEC33E-5F672C and LFECP33E-5F672C in Lattice's ispLEVER® 7.0 SP1 software. When using this IP core with different parameters, density, or speed grade within the LatticeECP/EC families, performance may vary.

Hardware Demo

A hardware demonstration bitstream for this IP core is available for use with the LatticeEC Advanced Evaluation Board. The bitstream, and a complete description of its operation is available for download by clicking the "Design Files" link in the resource box on this page.

Ordering Information

Part Numbers:

For LatticeECP/EC: DDRCT-GEN-E2-U6
For LatticeXP: DDRCT-GEN-XM-U6
For LatticeXP2: DDRCT-GEN-X2-U6
For LatticeSC: DDRCT-GEN-SC-U6
For LatticeECP2: DDRCT-GEN-P2-U6
For LatticeECP2M: DDRCT-GEN-PM-U6

To download the fully functional evaluation version of this IPexpress user configurable core, go to the Lattice IP Server tab in the ispLEVER IPexpress GUI window.

To find out how to purchase the DDR SDRAM Controller - Pipelined IP Core, please contact your local Lattice Sales Office.