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DDR SDRAM Controller - Pipelined

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Overview

IPexpress User Configurable LogoThe Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller that interfaces with industry standard DDR SDRAM. The memory controller provides a generic command interface to the user's application. This interface reduces the effort to integrate the module with the remainder of the application and minimizes the need to deal with the DDR SDRAM command interface. The timing parameters for the memory can be set through the signals that are input to the core as part of the configuration interface. This enables switching between different memory devices and modification of timing parameters to suit the application using the same netlist.

DDR SDRAM Controller - Pipelined Block Diagram

Features

  • Interfaces to Industry Standard DDR SDRAM
  • High-performance DDR1 400/333/266/200/133 operation for LatticeECP3™, LatticeECP2/M, LatticeECP2/MS, LatticeSC™, LatticeSCM™, and LatticeXP2™ devices; and DDR1 333/266/200/133 operation for LatticeECP™, LatticeEC™ and LatticeXP™ devices
  • Programmable Burst Lengths of 2, 4 or 8
  • Programmable CAS Latency of 2 or 3 Cycles
  • Intelligent Bank Management to Minimize ACTIVE Commands
  • Supports All Standard DDR Commands
  • Synchronous Implementation for Reliable Operation
  • Command Pipeline to Maximize Throughput
  • Support for Two DIMM
  • Supports all Common Memory Configurations
    • SDRAM data path widths of 8, 16, 32, 64 and 72 bits
    • Variable address widths for different memory device
    • Up to 8 (DDR1) chip selects for multiple SO/DIMM support
    • Programmable timing parameters
    • Byte level writing through Data Mask signals

The DDR SDRAM Controller - Pipelined is available as an IPexpress user configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may be prevented or the bitstream may have time logic present unless a license for the IP is purchased.

Performance and Resource Utilization

LatticeECP31
Parameter Settings2 SLICEs LUTs Registers I/O fMAX (MHz)
User Guide Table 1 parameter defaults 1167 1384 1591 249 200MHz (400 DDR)

1.Performance and utilization characteristics are generated using LFE3-95E-8FN1156CES in Lattice ispLEVER 8.0 software. When using this IP core in a different density, speed or grade within the LatticeECP3 family, performance may vary.
2.SDRAM data path width of 32 bits.

LatticeECP2M/S1
Parameter Settings2 SLICEs LUTs Registers I/O fMAX (MHz)
User Guide Table 1 parameter defaults 1221 1408 1566 249 200MHz (400 DDR)

1.Performance and utilization characteristics are generated using LFECP2M-35E-6F672C in Lattice ispLEVER 8.0 software. When using this IP core in a different density, speed or grade within the LatticeECP2M/S family, performance may vary.
2.SDRAM data path width of 32 bits.

LatticeECP2/S1
Parameter Settings2 SLICEs LUTs Registers I/O fMAX (MHz)
User Guide Table 1 parameter defaults 1221 1408 1566 249 200 MHz (400 DDR)

1.Performance and utilization characteristics are generated using LFECP2-50E-6F672C in Lattice ispLEVER 8.0 software. When using this IP core in a different density, speed or grade within the LatticeECP2/S family, performance may vary.
2.SDRAM data path width of 32 bits.

LatticeECP & LatticeEC1
Parameter Settings2 SLICEs LUTs Registers I/O fMAX (MHz)
User Guide Table 1 parameter defaults 1320 1393 1768 249 166 MHz (333 DDR)

1.Performance and utilization characteristics are generated using LFECP33-5F672C in Lattice ispLEVER 8.0 software. When using this IP core in a different density, speed or grade within the LatticeECP/EC family, performance may vary.
2.SDRAM data path width of 32 bits

LatticeSC/M1
Parameter Settings2 SLICEs LUTs Registers I/O fMAX (MHz)
User Guide Table 1 parameter defaults 1087 1235 1511 237 200 MHz (400 DDR)

1.Performance and utilization characteristics are generated using LFSC3GA25E-6F900C in Lattice ispLEVER 8.0 software. When using this IP core in a different density, speed or grade within the LatticeSC/M family, performance may vary.
2.SDRAM data path width of 32 bits.

LatticeXP21
Parameter Settings2 SLICEs LUTs Registers I/O fMAX (MHz)
User Guide Table 1 parameter defaults 1219 1406 1566 249 200 MHz (400 DDR)

1.Performance and utilization characteristics are generated using LFXP2-17E-6F484C in Lattice ispLEVER 8.0 software. When using this IP core in a different density, speed or grade within the LatticeXP2 family, performance may vary.
2.SDRAM data path width of 32 bits.

LatticeXP1
Parameter Settings2 SLICEs LUTs Registers I/O fMAX (MHz)
User Guide Table 1 parameter defaults 1320 1393 1768 249 133 MHz (266 DDR)

1.Performance and utilization characteristics are generated using LFXP20E-5F484C in Lattice ispLEVER 8.0 software. When using this IP core in a different density, speed or grade within the LatticeXP family, performance may vary.
2.SDRAM data path width of 32 bits.

Hardware Demo

A hardware demonstration bitstream for this IP core is available for use with the LatticeEC Advanced Evaluation Board. The bitstream, and a complete description of its operation is available for download by clicking the "Design Files" link in the resource box on this page.

Ordering Information

Family Part Number
LatticeECP3 DDRCT-GEN-E3-U6
LatticeECP2M DDRCT-GEN-PM-U6
LatticeECP2 DDRCT-GEN-P2-U6
LatticeEC/P DDRCT-GEN-E2-U6
LatticeSC DDRCT-GEN-SC-U6
LatticeXP2 DDRCT-GEN-X2-U6
LatticeXP DDRCT-GEN-XM-U6


IP Express Version: 6.7
Evaluate: To download a full evaluation version of this IP, go to the Lattice IP Server tab in the IPexpress Main Window.  All ispLeverCORE IP cores and modules available for download are visible on this tab.
Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.