DDR/DDR2 SDRAM Controller MACO Core

The DDR/DDR2 Synchronous Dynamic Random Access Memory (SDRAM) Controller MACO Core is a general-purpose memory controller that interfaces with industry standard DDR/DDR2 SDRAM devices and modules. This IP core is an IPexpress configurable core that provides the flexibility for modifying data widths, burst transfer rates, and CAS latency settings in a design. It provides a simple command interface for application logic. The controller can be configured to function as a DDR only or DDR2 memory controller.

This proven DDR/DDR2 core is optimized utilizing MACO ASIC gates in the LatticeSCM devices, resulting in fast, small cores that utilize the latest architecture to its fullest.

• Interfaces to industry standard DDR and DDR2 SDRAM
• Programmable burst length of 4 or 8
• Posted CAS functionality
• ODT signal generation
• Programmable CAS latency of 3 or higher
• Intelligent bank management to minimize ACTIVE commands
• Synchronous implementation
• Command pipeline to maximize throughput
• Supports SDRAM data path widths of 8, 16, 32, 40, 64 and 72 bits. Data width of 72 is supported in flip-chip or wire bond packages only with single-ended DQS. Maximum data width with differential mode DQS is 40 in wire bond packages.

• Varying address widths for different memory devices
• Programmable timing parameters
• Internal core frequency and DDR-2 DRAM frequency of 333MHz with two chip selects used
• Byte-level writing through data mask signals
• Supports both true and complementary DQS during write (for a maximum of 40 data bits). During read, the complementary pin is unused.
• Maximum of two chip selects (includes the capability for both chip selects to be de-selected to allow for other chip selects to be added via FPGA gates)
• Supports PCB trace lengths of up to eight inches.