The Lattice Double Data Rate (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller that interfaces with industry standard DDR3 memory devices/modules compliant with JESD79-3, DDR3 SDRAM Standard, and provides a generic command interface to user applications. The DDR3 SDRAM is the next-generation DDR SDRAM memory technology which features faster speed, mitigated SSO, and reduced routing due to “fly-by” routing signals to SDRAM instead of low skew tree distribution. This core reduces the effort required to integrate the DDR3 memory controller with the remainder of the application and minimizes the need to directly deal with the DDR3 memory interface.
The DDR3 SDRAM Controller is available as an IPexpress user configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may be prevented or the bitstream may have time logic present unless a license for the IP is purchased.
| Parameters | SLICEs | LUTs | Registers | I/O | fMAX (MHz) |
|---|---|---|---|---|---|
| Data Bus Width: 8 (x8) | 1635 | 2368 | 1670 | 42 | 400 MHz (800 Mbps) |
| Data Bus Width: 16 (x8) | 1810 | 2505 | 1960 | 53 | 400 MHz (800 Mbps) |
| Data Bus Width: 24 (x8) | 1989 | 2641 | 2267 | 64 | 400 MHz (800 Mbps) |
| Data Bus Width: 32 (x8) | 2093 | 2640 | 2536 | 75 | 400 MHz (800 Mbps) |
| Data Bus Width: 40 (x8) | 2058 | 2671 | 2377 | 86 | 400 MHz (800 Mbps) |
| Data Bus Width: 48 (x8) | 2156 | 2734 | 2562 | 97 | 400 MHz (800 Mbps) |
| Data Bus Width: 56 (x8) | 2297 | 2865 | 2725 | 108 | 400 MHz (800 Mbps) |
| Data Bus Width: 64 (x8) | 2389 | 2978 | 2901 | 119 | 400 MHz (800 Mbps) |
| Data Bus Width: 72 (x8) | 2527 | 3122 | 3000 | 130 | 333 MHz (666 Mbps) |
1. Performance and utilization data are generated targeting an LFE3-150EA-8FN1156C device using Lattice Diamond 1.4 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family.
2. EA silicon support only.
3. The DDR3 IP core can operate at 400 MHz (800 DDR3) in the fastest speed-grade (-8, -8L, or -9) when the data width is 64 bits or less and one chip select is used.
| Family | Part Number |
|---|---|
| LatticeECP3 (EA) | DDR3-P-E3-U1 |
IP Version: 1.4
Evaluate: To download a full evaluation version of this IP, go to the IPexpress tool and click the IP Server button in the toolbar. All LatticeCORE IP cores and modules available for download will be visible. For more information on viewing/downloading IP please read the IP Express Quick Start Guide.
Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.
© Lattice Semiconductor Corporation 2012
