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Overview
Features
The DDR2 SDRAM Controller - Pipelined is available as an IPexpress user configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may be prevented or the bitstream may have time logic present unless a license for the IP is purchased.
Performance and Resource Utilization
1.Performance and utilization characteristics are generated using LFE3-95E-8FN1156CES in Lattice ispLEVER 8.0 software. When using this IP core in a different density, speed or grade within the LatticeECP3 family, performance may vary.
1.Performance and utilization characteristics are generated using LFECP2M-35E-6F672C in Lattice ispLEVER 8.0 software. When using this IP core in a different density, speed or grade within the LatticeECP2M/S family, performance may vary.
1.Performance and utilization characteristics are generated using LFECP2-50E-6F672C in Lattice ispLEVER 8.0 software. When using this IP core in a different density, speed or grade within the LatticeECP2/S family, performance may vary.
1.Performance and utilization characteristics are generated using LFSC3GA25E-6F900C in Lattice ispLEVER 8.0 software. When using this IP core in a different density, speed or grade within the LatticeSC/M family, performance may vary.
1.Performance and utilization characteristics are generated using LFXP2-17E-6F484C in Lattice ispLEVER 8.0 software. When using this IP core in a different density, speed or grade within the LatticeXP2 family, performance may vary.
Ordering Information
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