CPRI

Overview

The Lattice Common Public Radio Interface (CPRI) IP core together with SERDES and Physical Coding Sublayer (PCS) functionality integrated in the LatticeSC/M™ and LatticeECP2M™ FPGAs implements the physical layer of the CPRI specification and interleaves IQ data with synchronization, control and management information. It can be used to connect Radio Equipment Control (REC) and Radio Equipment (RE) modules.  

CPRI Block Diagram
[Click to enlarge]

Features

• Supports the physical link layer (Layer 1) of the CPRI specification
• Supports the three standard bit rates of the CPRI specification
  
  • 614.4 Mbps
  • 1228.8 Mbps
  • 2457.6 Mbps
• Supports 8b/10b encoding/decoding performed in the PCS/SERDES
• Supports code-violation detection performed in the PCS/SERDES
• Performs CPRI Hyperframe Framing
  
  • Performs interleaving of IQ data, sync, C&M data, and vendor specific information
  • Provides an 8-, 16-, or 32-bit parallel interface for IQ data
• Performs subchannel mapping:
  
  • Supports a slow C&M channel based on a serial HDLC interface at standard bit rates (240 Kbps, 480 Kbps,  960 Kbps, and 1920 Kbps). The HDLC framer, if needed, must be provided as a separate IP core.
  • Supports a fast C&M channel based on a serial Ethernet interface (84.48 Mbps max.) to the user logic and accepts a user selected pointer to the CPRI subchannel where the Ethernet link starts. The Ethernet MAC function must be provided as a separate IP core.
• Performs synchronization and timing as defined in section 4.2.8 of the CPRI Specification
• Supports the L1 Inband Protocol
• Provides a parallel interface for merging vendor specific data into the CPRI frame
• Supports Delay Calibration as defined in section 4.2.9 of the CPRI Specification
• Provides a start-up sequence state machine in hardware for both REC and RE nodes which performs:
  
  • Synchronization and Rate Negotiation
  • C&M Plane setup
• Performs Link Maintenance as defined in section 4.2.10 of the CPRI Specification:
  
  • LOS detection
  • LOF detection
  • RAI indication
• Optional top-level template that implements user registers for control and status management
• Optional 8-bit register interface via built-in LatticeSC System Bus

Low Latency option for ECP2M/S devices only

• Supports 1228.8 Mbps and 2457.6 Mbps line bit rates only
• FPGA bridge FIFOs in the SERDES/PCS block are bypassed in both the receive and transmit directions
• Logic blocks supporting receive direction 10b word alignment, 10b/8b decoding and core-violation detection in
  the SERDES/PCS are bypassed and the corresponding functions are implemented in FPGA gates 

Resource Utilization

¹ Resource utilization characteristics are in Lattice's ispLEVER 7.1 software with Synplify synthesis and targeting a LatticeSC LFSC3GA25E-5F900C device. When using this IP core in a different density, speed, or grade within the LatticeSC family or in a different software version, resource utilization may vary.  Precision synthesis is not available in this release but will be available in a future ispLEVER release.

¹ Resource utilization characteristics are in Lattice's ispLEVER 7.1 software with Synplify synthesis and targeting a LatticeECP2M LFE2M35E-5F672C device. When using this IP core in a different density, speed, or grade within the LatticeECP2M family or in a different software version, resource utilization may vary. Precision synthesis is not available in this release but will be available in a future ispLEVER release.

Ordering Information

Part Numbers:
For LatticeSC/M: CPRI-SC-U4
For LatticeECP2M/S: CPRI-PM-U4

To download a full evaluation version of this IP, please go to the Lattice IP Server tab in the IPexpress Main Window. All ispLeverCORE IP modules available for download are visible on this tab.  To find out how to purchase the CPRI IP Core, please contact your local Lattice Sales Office.