64 Bit PCI Target

Overview

Peripheral Component Interconnect (PCI) is a widely accepted bus standard that is used in many applications including telecommunications, embedded systems, high performance peripheral cards, and networking.

Lattice's PCI IP core provides an ideal solution that meets the needs of today's high performance PCI applications. It is fully compliant with the PCI Local Bus Specification, revision 2.2 for speeds up to 66MHz. The PCI core provides a customizable 32/64-bit master/target or target solution. The core bridges the gap between the PCI interface and a specific design application, providing an integrated PCI solution. The PCI solution allows designers to focus on the application rather than on the PCI specification, resulting in a faster time-to-market.

The Lattice PCI offering is available in a number of configurations covering 32-bit PCI, 64-bit PCI, 32-bit local bus, 64-bit local bus, master/target and target applications. In this document, details of 64-bit operation and master operation only apply when relevant. The appendix to the user's guide shows what cores are available on which devices.

Features

Available as 32/64-Bit PCI Bus and 32/64-Bit Local Bus PCI SIG Local Bus Specification, Revision 3.0 Compliant 64-Bit Addressing Support (Dual Address Cycle) Capabilities List Pointer Support Parity Error Detection Up to Six Base Address Registers (BARs)

Fast Back-to-Back Transaction Support Supports Zero Wait State Transactions Special Cycle Transaction Support Customizable Configuration Space Up to 66MHz PCI Fully Synchronous Design

 

Performance and Resource Utilization

LatticeECP3¹

Bus Width	IPexpress Mode	Slices	LUTs	Registers	sysMEM EBRs	External Pins	fMAX (MHz)
64-bit	Target 33 MHz	612	918	592	-	87	33
64-bit	Target 66 MHz	809	1341	612	-	87	66

1. Performance and utilization data are generated using an LFE3-95EA-7FN1156CES device with Lattice Diamond 1.0 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family.

LatticeECP2M¹

Bus Width	IPexpress Mode	Slices	LUTs	Registers	sysMEM EBRs	External Pins	fMAX (MHz)
64-bit	Target 33 MHz	722	927	594	-	87	33
64-bit	Target 66 MHz	832	1350	614	-	87	66

1. Performance and utilization data are generated using an LFE2M-35E-6F672C device with Lattice Diamond 1.0 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2M family.

LatticeECP2¹

Bus Width	IPexpress Mode	Slices	LUTs	Registers	sysMEM EBRs	External Pins	fMAX (MHz)
64-bit	Target 33 MHz	722	927	594	-	87	33
64-bit	Target 66 MHz	832	1350	614	-	87	66

1. Performance and utilization data are generated using an LFE2-20E-6F672C device with Lattice Diamond 1.0 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2 family.

 

LatticeEC/P¹

Bus Width	IPexpress Mode	Slices	LUTs	Registers	sysMEM EBRs	External Pins	fMAX (MHz)
64-bit	Target 33 MHz	715	913	594	-	87	33
64-bit	Target 66 MHz	832	1344	614	-	87	66

1. Performance and utilization data are generated using an LFEC33E-5F672C device with Lattice Diamond 1.0 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP/EC family.

 

LatticeSC¹

Bus Width	IPexpress Mode	Slices	LUTs	Registers	sysMEM EBRs	External Pins	fMAX (MHz)
64-bit	Target 33 MHz	621	893	594	-	87	33
64-bit	Target 66 MHz	845	1391	622	-	87	66

1. Performance and utilization data are generated using an LFSC3GA25E-6F900C device with Lattice Diamond 1.0 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeSC family.

 

LatticeXP2¹

Bus Width	IPexpress Mode	Slices	LUTs	Registers	sysMEM EBRs	External Pins	fMAX (MHz)
64-bit	Target 33 MHz	707	919	592	-	87	33
64-bit	Target 66 MHz	827	1342	612	-	87	66

1. Performance and utilization data are generated using an LFXP2-17E-6F484C device with Lattice Diamond 1.0 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeXP2 family.

LatticeXP¹

Bus Width	IPexpress Mode	Slices	LUTs	Registers	sysMEM EBRs	External Pins	fMAX (MHz)
64-bit	Target 33 MHz	715	913	594	-	87	33
64-bit	Target 66 MHz	832	1344	614	-	87	66

1. Performance and utilization data are generated using an LFXP20C-5F484C device with Lattice Diamond 1.0 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeXP family.

 

Ordering Information

Family	Bus Width	Bus Speed	Target Part Number
LatticeECP3	64-bit	33MHz, 66MHz	PCI-T64-E3-U6
LatticeECP2M	64-bit	33MHz, 66MHz	PCI-T64-PM-U6
LatticeECP2	64-bit	33MHz, 66MHz	PCI-T64-P2-U6
LatticeECP/EC	64-bit	33MHz, 66MHz	PCI-T64-E2-U6
LatticeSC	64-bit	33MHz, 66MHz	PCI-T64-SC-U6
LatticeXP2	64-bit	33MHz, 66MHz	PCI-T64-X2-U6
LatticeXP	64-bit	33MHz, 66MHz	PCI-T64-XM-U6

IP Version: PCI Target 33MHz = 6.5, PCI Target 66MHz = 6.3
Evaluate: To download a full evaluation version of this IP, go to the Lattice IP Server tab in the IPexpress Main Window. All ispLeverCORE IP cores and modules available for download are visible on this tab.  *PCI cores for ORCA and ispXPGA,devices are supported by the Lattice factory-configurable design flow.
Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.