The 2.5Gb MAC core can support data rates of 1Gbps or 2.5Gbps in LatticeSC/M™ devices. The 2.5Gb MAC transmits and receives data between a host processor and an Ethernet network. The main function of the Ethernet MAC is to ensure that the Media Access rules specified in the 802.3 IEEE standards are met while transmitting and receiving Ethernet frames.
The data received from the GMII interface is first buffered until sufficient data is available to be processed by the Receive MAC (Rx MAC). The Preamble and the Start of Frame Delimiter (SFD) information are then extracted from the incoming frame to determine the start of a valid frame. The Receive MAC checks the address of the received packet and validates whether the frame can be received before transferring it into the FIFO. Only valid frames are transferred into the FIFO. The 2.5Gb MAC however always calculates CRC to check whether the frame was received error-free or not.

The 2.5Gb MAC is a user-configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may be prevented or the bitstream may have time logic present unless a license for the IP is purchased.
| Mode | SLICEs | LUTs | Registers | sysMEM EBRs | fMAX (MHz) |
|---|---|---|---|---|---|
|
With MIIM_module |
1008 |
1428 |
1032 |
1 |
125(-5, -6) / 312.5(-7) |
|
Without MIIM_module |
1168 |
1606 |
1186 |
1 |
125(-5, -6) / 312.5(-7) |
Part Numbers:
For LatticeSC/M: 2PT5-MAC-SC-U1
To download a full evaluation version of this IP, please go to the Lattice IP Server tab in the IPexpress Main Window. All ispLeverCORE IP modules available for download are visible on this tab.
To find out how to purchase the 2.5Gb MAC IP Core, please contact your local Lattice Sales Office.