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10Gb+ Ethernet MAC

In Detail

Overview

IPexpress User Configurable Logo The 10Gb+ Ethernet Media Access Controller (MAC) transmits and receives data between a host processor and an Ethernet network. The main function of the 10Gb+ Ethernet MAC is to ensure that the Media Access rules specified in the IEEE802.3ae standard are met while transmitting a frame of data over Ethernet. On the receive side, the Ethernet MAC extracts the different components of a frame and transfers them to higher applications through a FIFO interface.

10 GbE IP Interface

Features

  • Compliant to IEEE 802.3-2005 standard, successfully passed University of New Hampshire InterOperability Laboratory(UNH-IOL) 10GbE MAC hardware tests
  • Supports standard 10Gbps Ethernet link layer data rate
  • Supports rates up to 12Gbps by over-clocking
  • 64-bit wide internal data path operating at 156.25MHz to 187.5MHz
  • XGMII interface to the PHY layer (using IODDR external to the core)
  • XAUI interface to the PHY layer (using PCS/SERDES external to the core)
  • Simple FIFO interface with user's application
  • Optional Multicast address filtering
  • Transmit and receive statistics vector
  • Optional statistics counters of length from 16 to 40 bits for all devices (statistic counters are external to the core)
  • Programmable Inter Frame Gap
  • Supports:
    • Full duplex operation
    • Flow control using PAUSE frames
    • VLAN tagged frames
    • Automatic padding of short frames
    • Optional FCS generation during transmission
    • Optional FCS stripping during reception
    • Jumbo frames up to 16k
    • Inter frame Stretch Mode during transmission
    • Deficit Idle Count

 

Performance and Resource Utilization

LatticeECP31
Mode SLICEs LUTs Registers External Pins2 sysMEM EBRs fMAX (MHz)
Multicast Address Filtering 3106 4184 2823 78 4 169

1.Performance and utilization characteristics are in Lattice ispLEVER 8.0 software with Synplify Pro C-2009.03L-1 synthesis and targeting a LatticeECP3 LFE3-70EA-8F1156CES device. When using this IP core in a different density, speed, or grade within the LatticeECP3 family or in a different software version, performance may vary.
2.The 10Gb+ Ethernet MAC core itself does not use any external pins. However, in an application the core is used together IODDR and I/O Buffers integrated in the LatticeECP3 series FPGA. Thus the application implementing the 10Gb+ Ethernet MAC specification will utilize I/O pins.

LatticeECP2M/S1
Mode SLICEs LUTs Registers External Pins2 sysMEM EBRs fMAX (MHz)
Multicast Address Filtering 3216 4420 2826 78 4 167

1.Performance and utilization characteristics are in Lattice ispLEVER 8.0 software with Synplify Pro C-2009.03L-1 synthesis and targeting a LatticeECP2M LFE2M/S35E-7F672C device. When using this IP core in a different density, speed, or grade within the LatticeECP2M/S family or in a different software version, performance may vary.
2.The 10Gb+ Ethernet MAC core itself does not use any external pins. However, in an application the core is used together IODDR and I/O Buffers integrated in the LatticeECP2M series FPGA. Thus the application implementing the 10Gb+ Ethernet MAC specification will utilize I/O pins.

LatticeECP2/S1
Mode SLICEs LUTs Registers External Pins2 sysMEM EBRs fMAX (MHz)
Multicast Address Filtering 3216 4420 2826 78 4 163

1.Performance and utilization characteristics are in Lattice ispLEVER® 8.0 software with Synplify Pro C-2009.03L-1 synthesis and targeting a LatticeECP2 LFE2-35E/S-7F672C device. When using this IP core in a different density, speed, or grade within the LatticeECP2/S family or in a different software version, performance may vary.
2.The 10Gb+ Ethernet MAC core itself does not use any external pins. However, in an application the core is used together IODDR and I/O Buffers integrated in the LatticeECP2 series FPGA. Thus the application implementing the 10Gb+ Ethernet MAC specification will utilize I/O pins.

LatticeSC/M1
Mode SLICEs LUTs Registers External Pins2 sysMEM EBRs fMAX (MHz)
Multicast Address Filtering 2897 4276 2780 78 4 219

1. Performance and utilization characteristics are in Lattice ispLEVER 8.0 software with Synplify Pro C-2009.03L-1 synthesis and targeting a LatticeSC LFSC3GA25E-5F900C device. When using this IP core in a different density, speed, or grade within the LatticeSC family or in a different software version, performance may vary.
2. The 10Gb+ Ethernet MAC core itself does not use any external pins. However, in an application the core is used together IODDR and I/O Buffers integrated in the LatticeSC series FPGA. Thus the application implementing the 10Gb+ Ethernet MAC specification will utilize I/O pins.

Ordering Information

Family Part Numbers
LatticeECP3 ETHER-10G-E3-U4
LatticeECP2M ETHER-10G-PM-U4
LatticeECP2 ETHER-10G-P2-U4
LatticeSC/M ETHER-10G-SC-U4


IP Version: 4.2
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