EP501: NAND Flash Controller

The EP501 NAND Flash controller provides an easy interface for user to access NAND Flash devices. Typical NAND Flash devices are accessed through complicated sequence of command, address, data, and confirmation protocols. The EP501 manages all the hardware protocols and allows the user to access NAND Flash memory simply by reading and writing control registers inside the EP501.

A very large size of NAND Flash memory can be accessed through a small number of control registers. The NAND Flash controller occupies only a small size in the system's memory space without scarifying system performance. Burst access to the NAND Flash memory is supported by the controller at full memory bandwidth. Timing parameters of the controller is fully programmable so different memory speeds are supported regardless of the operating frequency of the controller.

Implementation Results

The following are typical performance and utilization results.

Features

• Supports up to 4 banks of NAND Flash devices.
• Each bank contains up to 5 NAND Flash connected in parallel for a total of 20 NAND Flash devices.
• Simple user interface designed for easy on-chip integration.
• Options to provide PCI, AMBA AHB, PCMCIA, Cardbus or CompactFlash bus interface.
• Large Flash memory space can be accessed using data and index register method.
• Programmable access timing, NAND Flash size, data width and number of banks.
• Supports large block and small block NAND Flash devices.
• User has full access to spare data in NAND Flash device.
• Optional single-bit correction double bit detection error correction code (ECC).
• Option to apply ECC protection on per word or per page basis.
• Error logging with ECC correction and detection.
• Interrupt generation based on ECC error.
• Designed for ASIC and FPGA implementations.
• Fully static design with edge-triggered flip-flops.