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The DSPI_FIFO is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signal SCK.
The DSPI_FIFO allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communications in a multi-master system. A serial clock line (SCK) synchronizes shifting and
sampling of the information on the two independent serial data lines. DSPI_FIFO data are simultaneously transmitted and received.
The DSPI_FIFO is a technology independent design that can be implemented in a variety of process technologies
The DSPI_FIFO system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as a master or a slave device. Data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of eight different bit rates for the serial clock.
The DSPI_FIFO automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS7O - SS0O), and address SPI slave device to exchange serially shifted data. Error-detection logic is included to support interprocessor communications. A write-collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple-master mode-fault detector automatically disables DSPI_FIFO output drivers if more than one SPI devices simultaneously attempts to become bus master.
The DSPI_FIFO supports two DMA modes: single transfer and multi-transfer. These modes allow DSPI_FIFO to interface to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers.
DSPI_FIFO is fully customizable, which means it is delivered in the exact configuration to meet users' requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.
The following are typical performance and utilization results.
Two DMA Modes allows single and multitransfer
In the FIFO mode transmitter and receiver are each buffered with 16/64 byte FIFO's to reduce the number of interrupts presented to the CPU
Optional FIFO size extension to 128, 256 or 512 Bytes
Fully synthesizable, static synchronous design with no internal tri-states