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Document contains brief description of DF6811CPU core functionality. The DF6811CPU is a advanced 8-bit MCU IP Core. DF6811CPU soft core is binary-compatible with the industry standard 68HC11 8-bit microcontroller and can achieve a performance of up to 45-100 million instruc-tions per second in today's integrated circuit technologies. DF6811CPU has FAST architecture that is 3.8 times faster compared to original implementation.
Self-monitoring circuitry is included on-chip to protect against system errors. An illegal opcode detection circuit provides a non-maskable interrupt when illegal opcode detected.
Two software-controlled power-saving modes, WAIT and STOP, are available to conserve additional power. These modes make the DF6811CPU IP Core especially attractive for automotive and battery-driven applications.
The DF6811CPU have built in the development support features designed into DF6811CPU. The LIR signal is intended as a debugging aid. This signal is driven to active low for the first bus cycle of each new instruction, making it easy to reverse assemble (disassemble) instructions from the display of a logic analyzer.
DF6811CPU is fully customizable, which means it is delivered in the exact configuration to meet users requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.
The following are typical performance and utilization results.
| Device | Speed grade | Fmax | LUTs | PFUs |
|---|---|---|---|---|
| XP | -5 | 39 MHz | 2598 | 374 |
| ECP | -5 | 42 MHz | 2598 | 374 |
| ECP | -5 | 42 MHz | 2598 | 374 |
| ORCA 4 | -3 | 34 MHz | 2504 | 404 |
© Lattice Semiconductor Corporation 2013
