SPI_MS: Serial Peripheral Interface Master/Slave Core

Download the datasheet

The Serial Peripheral Interface (SPI) allows high-speed synchronous serial data transfers between microprocessors, microcontrollers and peripheral devices. The SPI_MS core implements the Serial Peripheral Interface, which can operate either as a master or as a slave.

When operating in master mode, the core generates the serial data clock (SCK) and selects the slave device, which will be addressed. When operating in slave mode, another master device generates the serial data clock and activates the slave select input of the core, in order to communicate.

The core was carefully designed to provide the most reliable communication possible, and to achieve very high bit rates.

Developed for easy reuse, the SPI_MS is available optimized for several Lattice devices, with competitive utilization and performance characteristics.

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Implementation Results

The following are typical performance and utilization results.

Features

• Fully synchronous design with one clock domain
• Fully duplex, synchronous, 8-bit serial data transfer
• High bit rates
• Master or slave mode
• Bit rates generated in Master mode: ÷2, ÷4, ÷8, ÷16, ÷32, ÷64, ÷128, ÷256 of the system clock
• Bit rates supported in Slave mode: fSCK ≤ fSYSCLK ÷2
• Eight Slave Select lines
• MSB first or LSB first data transfer
• Post-synthesis EDIF netlist optimized for a specific Lattice device (HDL RTL source code also available)

Applications

• Embedded microprocessor boards and SOCs
• Consumer and professional audio/video
• Home and automotive radio