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The SDLC controller is a synthesizable HDL core providing a high-speed synchronous serial communication interface.
Operation of the controller is similar to that used in the Intel 8XC152 Global Serial Channel (GSC)working in SDLC mode under a CPU control. Communication with the CPU is realized through Special Function Registers (SFRs)and three interrupt sources. This allows the SDLC controller to be easy integrated with any CPU core.
The design is strictly synchronous,with positive-edge clocking,no internal tri-states and a synchronous reset.
The following are typical performance and utilization results.
| ispXPGA Device | LUT-4s | Registers | PFUs | SysMEM EBRs |
External I/Os |
Speed (fmax, MHz) |
|---|---|---|---|---|---|---|
| LFX125C-4 |
4398 |
1568 |
411 |
2 |
39 |
81.0 |
| ORCA4 Device | LUT-4s |
Registers |
PFUs |
SysMEM EBRs |
External I/Os |
Speed (fmax, MHz) |
| OR4E02-3 |
1096 |
346 |
152 |
2 |
39 |
89.5 |
| LatticeECP2 Device | LUT-4s | Registers | PFUs | SysMEM EBRs |
External I/Os |
Speed (fmax, MHz) |
|
LFE2-50-7 |
653 |
344 |
457 |
2 |
39 |
155 |
|
LatticeECP2M Device |
LUT-4s | Registers | PFUs | SysMEM EBRs |
External I/Os |
Speed (fmax, MHz) |
|
LFE2M-35E-7 |
596 |
344 | 416 | 2 | 39 |
156 |
| LatticeSC Device | LUT-4s | Registers | PFUs | SysMEM EBRs |
External I/Os |
Speed (fmax, MHz) |
| LGSC3GA-25E-7 |
2528 |
344 |
400 |
2 |
39 |
219 |
|
LatticeXP2 Device |
LUT-4s | Registers | PFUs | SysMEM EBRs |
External I/Os |
Speed (fmax, MHz) |
| LFXP2-17E-7 |
640 |
344 |
454 |
2 |
39 |
120 |
© Lattice Semiconductor Corporation 2012
