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CAN: Bus Controller Core

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The development of increasingly complex microsystems requires the usage of a powerful field bus system for distributed real-time networks. The CAN protocol has a wide acceptance in the field of serial communication.

The CAN bus controller core is described at the RTL system level which allow easy targeting of various technologies.

The CAN bus core is founded on the basic CAN principle and meets all constraints of the CAN-specification 2.0B. For buffering of received or transmitted messages three 13-byte buffers are used. In practice no overload frames will be generated.

CAN: Bus Controller Core

Implementation Results

The following are typical performance and utilization results.

Lattice Device LUT-4s Registers PFUs SysMEM
EBRs		 External
I/Os		 Speed
(fmax, MHz)
LFX1200B-51 1645 418 496 - 108 38
LFX1200B-5 1729 373 513 5 32 33
Lattice Device LUT-4s Registers Slices SysMEM
EBRs		 External
I/Os		 Speed
(fmax, MHz)
LFEC20E-52 1619 180 800 5 49 40
LFXP10-C-51 1279 189 712 - 125 48
LFXP2-17E-72 1352 179 818 5 49 61
LFE2-50-71 1359 178 796 - 125 65
LFSC3GA25-71 1297 179 746 - 125 97
LCMXO2280C-51 1483 179 929 - 125 40

Notes: 1) results excluding memory 2) results with memory implemented in BRAM

Features

  • Implementation of the Basic CAN specification
  • No generated Overload Frames
  • Receiving and transmitting of both identifiers (CAN specification 2.0B)
  • Programmable data rate up to 1 mbps
  • Programmable baud rate prescaler (up to 1/30)
  • Application specific interface to the host-controller
  • Link to commercial bus drivers (for instance PCA82C250T by Philips)
  • Certified by Bosch reference model
  • The CAN Controller synthesizes to approximate 6500 gates

Applications

The core is suitable for implementing a wide range of digital signal processing applications.