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These issues can be addressed with the use of two special signal processing functions to precondition the RF signal to amplify - Crest Factor Reduction (CFR) and Digital Predistortion (DPD). However, near antenna logic for MIMO-based RRH systems were implemented using high end, premium FPGAs which typically resulted in high power and cost forcing vendors to sacrifice design flexibility and attempt expensive ASIC conversions.
This solution supports the integration of all RRH processing into a single mid-range, low-power, low-cost LatticeECP3 FPGA device. The solution also delivers the lowest dynamic power for programmable logic DPD solution at 400mW per antenna. This makes it ideal for various wireless applications including WCDMA, LTE, WiMAX/WiBro, TD-SCDMA, DVB-T/S/H.
Ordering InformationFor more information on the RRH solution or for pricing and availability please contact Affarii. |
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