ORSPI4

ORSPI4: Embedded SPI4.2 Cores, 3.7Gbps SERDES, High-Speed Memory Controller and FPGA

• Lowest power programmable SPI4.2 solution today!
• Over 1 million gates of IP embedded in ASIC core - improves performance and efficiency
• Best SERDES in Industry

Introducing the ORCA® ORSPI4, a next-generation FPSC from Lattice Semiconductor. The ORSPI4 device offers a fast and flexible solution for high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORSPI4 device contains two OIF-compliant System Packet Interface, Level 4, Phase 2 (SPI4.2) interface blocks, high-speed memory controller, 4 channels of 600 Mbits/s to 3.7 Gbits/s SERDES with 8b/10b encoding/decoding, and over 16K programmable logic elements... all on a single chip! The programmable logic elements can be used to implement functions (e.g. CSIX, PL3, UT3, etc.) to interface to other devices on a board. The embedded SPI4.2 cores consume less than 2W at 900Mbps operations. This is less than one-fifth the power consumption of competitive solutions implemented in FPGA gates!

The embedded SPI4.2 blocks provide dual 10 Gbits/s Physical-to-Link Layer interfaces in conformance to the OIF-SPI4-02.0 specification. An independent memory controller block is also embedded to provide for data buffering between the FPGA logic and external memory. This high-speed memory controller supports a throughput of greater than 20 Gbits/s. A high-speed SERDES block supports four serial links, each operating at up to 3.7 Gbits/s (2.96 Gbits/s data rate with 8b/10b encoding and decoding). The SERDES block provides four full-duplex synchronous interfaces with built-in Rx Clock and Data Recovery (CDR) and transmitter pre-emphasis. The SERDES block is identical to that in Lattice's ORT82G5 device and supports embedded 8b/10b encoding/decoding and implements link state machines for both 10 Gbits/s Ethernet, and Fibre Channel.

Features

SPI4.2 Features

• OIF-SPI4-02.0 compliant interfaces
• Dynamic timing receive interface w/bandwidth up to 450MHz DDR (900Mbps)
• Static timing receive interface w/speeds up to 350 MHz DDR (700 Mbps)
• Transmit interface w/speeds up to 450 MHz DDR (900 Mbps)
• 256 logical ports with embedded Calendar-based sequence port polling mechanism and bandwidth allocation; shadow Calendar support for smooth transition to new Calendar
• Simple FIFO interface to the FPGA logic enables ease of design and built-in clock domain transfers
• Configuration options as suggested in the OIF-SPI4-02.0 standard to configure parameters such as maximum burst size, calendar length, main and shadow calendars (1K deep each), length of training sequence etc.
• Loopback modes provide system- and chip-level debug
• Full-rate SPI4.2 interface running at 450MHz DDR (900Mbits/sec) consumes less than 2W of power or less. Much more efficient than FPGAs with soft-IP SPI4.2 solutions which can burn power in excess of 10W
• Interoperability simulations completed with ORSPI4 partners (NPU and framer vendors)

Additional Embedded Core Features

• Quad 600 Mbits/s to 3.7 Gbps SERDES supports IEEE 802.3ae XAUI (Link State Machine & Alignment FIFOs embedded) and ANSI X3.230:1994 1G/2G FC-compliant (Link State Machine & Alignment FIFOs embedded)
• Proven performance (same SERDES used in ORT82G5 FPSC)
• QDR II memory interface provides 20+ Gbps bandwidth w/simple FIFO interface to FPGA. Proven performance with multiple memory suppliers.

Application Example:

The ORSPI FPSC is ideal for aggregating 2.5Gb streams via PL-3 to 10Gb streams for processing by a 10Gb Network Processor and switch fabric. The soft PL-3 IP cores reside in FPGA gates while the SPI4.2 cores are implemented in embedded ASIC logic. This implementation offers easier design and lower power consumption than FPGA implementations with SPI4.2 IP cores.

Lattice IP Cores and Reference Designs

FPSC design is supported by a variety of pre-tested, reusable functions optimized for the ORSPI4 architecture. Browse the See Also section of this page for ispLeverCORE Connection Partner links.

Lattice IP Cores

• Convolutional Encoder
• CSIX Level 1
• CSIX to PI40
• DDR SDRAM Controller - Non-Pipelined
• Ethernet MAC Cores
• Multi-channel DMA Controller
• Quad SPI-3 to SPI-4 Link Layer Bridge
• Quad SPI-3 to SPI-4 PHY Layer Bridge
• Reed-Solomon Decoder
• Reed-Solomon Encoder
• Turbo Decoder
• Turbo Encoder

Lattice Reference Designs

• 8b/10b Encoder/Decoder
• DDR SDRAM Controller
• QDR Memory Controller

ORSPI4 Evaluation Boards

The Lattice ORSPI4 Evaluation Board provides an evaluation and development platform for the Lattice ORSPI4 device. This full-featured board contains all the features you need to evaluate the ORSPI4 device, or aid in your development process.

View the ORSPI4 Evaluation Board webpage.