FPSCs from Lattice: ORSO82G5/42G5

Lattice Semiconductor has developed a next-generation FPSC intended for high-speed serial SONET backplane data transmission. Built on the ORCA Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORSO82G5 includes eight backplane transceiver channels, each operating at up to 2.7 Gbits/s data rate, providing a full-duplex synchronous interface with built-in Clock/Data Recovery (CDR) and more than 400k usable FPGA functional gates.

The ORSO42G5 includes four backplane transceiver channels, each operating at up to 2.7 Gbits/s data rate, along with more than 400K FPGA functional gates.

Both the ORSO82G5 and ORSO42G5 provide a full 10 Gbits/s backplane data connection with protection between a line card/redundant line card and switch fabric/redundant switch fabric. The FPGA portion can be used to implement a 2.5Gbit/s or 10Gbit/s SONET-based switch fabric interfaces.

Both the ORSO82G5 and ORSO42G5 provide a SERDES-based high-speed interface for inter-device communication on a board or across a backplane. The built-in clock recovery of these devices support higher system performance, easier-to-design clock domains in a multi-board system, and fewer signals on the backplane.

The ORSO82G5 and ORSO42G5 support SONET data scrambling and descrambling, streamlined SONET framing, transport overhead handling, cell insertion and extraction, idle cell insertion/deletion plus the programmable logic to terminate the network into proprietary systems. All SONET functionality is hidden from the user and no prior networking knowledge is required.

ORSO82G5/ORSO42G5 Products

The ORSO42G5 offers 4 Full Duplex Channels each at 2.7 Gbits/sec

Features

Embedded Core Features

• High-speed SERDES programmable serial data rates of 0.6 Gbits/s to 2.7 Gbits/s.
• Provides a 10 Gbits/s backplane interface to switch fabric with protection.
• Error-free operation demonstrated at 2.5 Gbits/s across 40 inches of FR-4 backplane and two connectors.
• Transmit pre-emphasis (programmable) for improved receive data eye opening.
• No knowledge of SONET/SDH needed in generic applications. Simply supply data (125 MHz-168.75 MHz clock) and an optional frame pulse.
• Eight-channel HSI function provides 2.7 Gbits/s serial user data interface per channel for a total chip bandwidth of >20 Gbits/s (full duplex).
• FIFOs optionally align incoming data across groups of two, four, or eight channels.
• In-band management through transport overhead insertion and extraction. Options to insert SONET TOH bytes or have them automatically inserted with default values.
• Programmable enable of SONET scrambler/ descrambler.
• Two 4K x 36 dual-port RAMs with access to the programmable logic.
• Optional byass of SONET frames for raw data interface to the FPGA logic.
• Optional Cell Mode available that uses SONET for physical layer and cells inserted as payload.
  • Multiple fixed-lengh cell payload sizes available (64, 68, 72 or 80 bytes)
  • Cell generation and insertion into payload on Tx
  • Cell extraction and error checking on Rx
  • Automatic idle cell generation and deletion for rate matching
  • Available in quad 2-link or single 8-link modes

Easy System Integration

Programmable platform for bridging network processor/routing devices to switch fabrics over SONET SERDES. On the line side, the ORSO82G5 can be utilized to provide a flexible interface to various optical modules (such as VSR-3).

Programmable Features

• High Performance ORCA Series 4 FPGA Gates.
• Internal performance of > 250 MHz.
• Over 400k usable functional gates.
• 1.5 V operation (30% less power than 1.8 V operation).
• Comprehensive I/O selections including LVTTL, LVCMOS, GTL, GTL+, PECL, SSTL3/2, HSTL, ZBT, DDR, LVDS, bused-LVDS, and LVPECL.

Lattice IP Cores and Reference Designs

FPSC design is supported by a variety of pre-tested, reusable functions optimized for the ORSO82G5/42G5 architecture. Browse the See Also section of this page for ispLeverCORE Connection Partner links.

Lattice IP Cores

• Convolutional Encoder
• CSIX Level 1
• CSIX to PI40
• DDR SDRAM Controller - Non-Pipelined
• Ethernet MAC Cores
• Multi-channel DMA Controller
• Reed-Solomon Decoder
• Reed-Solomon Encoder
• Turbo Decoder
• Turbo Encoder

Lattice Reference Designs

• 8b/10b Encoder/Decoder
• DDR SDRAM Controller
• QDR Memory Controller
• Telecom Bus Bridge for SONET Cross Connect

ORSO82G5 Evaluation Boards

The ORSO82G5 High-Speed SERDES Briefcase Board includes a number of features to help the user thoroughly evaluate the performance of the ORSO82G5 device, or aid in the development of custom designs. The board features numerous I/O connections, SMA connectors for high-speed signaling, on-board clocks (external clocks can be provided), on-board power management, and more.

View the ORSO82G5 High-Speed SERDES Briefcase Board webpage.

ORSO42G5 Evaluation Boards

The Lattice ORSO42G5 Evaluation Board provides an evaluation and development platform for the Lattice ORSO42G5 device. This versatile board contains all the features you need to evaluate the ORSO42G5 device, or aid in your development process.

View the ORSO42G5 Evaluation Board webpage.