FPSCs From Lattice

Lattice Semiconductor pioneered the approach of putting ASIC embedded cores and FPGA gates on the same silicon die. We call this a Field Programmable System Chip (FPSC). In contrast to ASICs with embedded FPGA gates, FPSCs have a broad range of uses. The embedded cores hold industry-standard Intellectual Property - bus interface, high-speed line interface, and high-speed transceiver cores. When these embedded cores are combined with hundreds of thousands of programmable gates they can be used in a variety of advanced system designs.

FPSC Product Selector Guide

	FPGA Technology	PFUs	FPGA System Gates (K)1	Embedded RAM bits (K)	Max User I/O	SERDES	User PLLs
ORSPI4	ORCA Series 4	2024	471-899	148	498		4
Embedded Core Function: OIF-SPI4-02.0 compliant 10 Gbits/s interfaces; backplane transceivers containing four channels, each operating up to 3.7 Gbits/s; high-speed memory controller.
ORLI10G	ORCA Series 4	1296	333-643	111	316	-	4
Embedded Core Function: OIF standard (OIF 99.102.5) compliant XSBI 10 Gbits/s transmit and 10 Gbits/s receive line interface.
ORT82G5/42G5	ORCA Series 4	1296	333-643	111	372/204		4
Embedded Core Function: Backplane transceivers containing eight (ORT82G5) or four (ORT42G5) channels, each operating at up to 3.7 Gbits/s, with a full-duplex synchronous interface with built-in Clock and Data Recovery (CDR).
ORT8850L	ORCA Series 4	624	201-397	74	278		4
Embedded Core Function: Backplane transceivers containing eight channels, each operating at up to 850 Mbits/s (6.8 Gbits/s when all eight channels are used) full duplex synchronous interface with built-in Clock and Data Recovery (CDR).
ORT8850H	ORCA Series 4	2024	471-899	148	297		4
Embedded Core Function: Backplane transceivers containing eight channels, each operating at up to 850 Mbits/s (6.8 Gbits/s when all eight channels are used) full duplex synchronous interface with built-in Clock and Data Recovery (CDR).
ORSO82G5/42G5	ORCA Series 4	1296	333-643	111	372/204		4
Embedded Core Function: SONET backplane transceivers containing eight (ORSO82G5) or four (ORSO42G5) channels, each operating at up to 2.7 Gbits/s, with a full-duplex synchronous interface with built-in Clock and Data Recovery (CDR).

¹FPGA System Gate Refers to:

• The embedded core, embedded system bus, FPGA interface and MPI are not included in the FPGA System Gate counts.
• The System Gate ranges are derived from the following:
• Minimum System Gates assumes 100% of the PFU's are used for logic only (No PFU RAM) with 40% EBR usage and 2 PLL's.
• Maximum System Gates assumes 80% of the PFU's are for logic, 20% are used for PFU RAM, with 80% EBR usage and 6 PLL's.