The LatticeXP2 flexiFLASH architecture combines a Look-Up Table (LUT) based FPGA fabric with Flash non-volatile cells. The flexiFLASH approach provides benefits such as instant-on, small footprint, on-chip storage with FlashBAK embedded block memories and Serial TAG memory and design security. The family also supports Live Updates with TransFR, 128-bit AES Encryption and Dual-Boot technologies. The LatticeXP2 FPGA fabric utilizes an underlying LatticeECP2 architecture that was optimized from the outset with high performance and low cost in mind. The LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O and enhanced sysDSP blocks.
|Distributed RAM (Kbits)||10||18||35||56||83|
|EBR SRAM (Kbits)||166||221||276||387||885|
|EBR SRAM Blocks||9||12||15||21||48|
|Maximum Available I/O||172||201||358||472||540|
|132-pin csBGA (8 x 8 mm)||86||86|
|144-pin TQFP (20 x 20 mm)||100||100|
|208-pin PQFP (28 x 28 mm)||146||146||146|
|256-ball ftBGA (17 x 17 mm)||172||201||201||201|
|484-ball fpBGA (23 x 23 mm)||358||363||363|
|672-ball fpBGA (27 x 27 mm)||472||540|
Development Boards and Kits are available to help you evaluate the LatticeXP2 technology, or aid in the development of your own design. Each board includes example designs, schematics and other resources to help you accelerate the evaluation and development process.